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PIC18F2450/4450 Data Sheet
28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
(c) 2006 Microchip Technology Inc.
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DS39760A
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS39760A-page ii
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(c) 2006 Microchip Technology Inc.
PIC18F2450/4450
28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
Universal Serial Bus Features:
* USB V2.0 Compliant * Low speed (1.5 Mb/s) and full speed (12 Mb/s) * Supports control, interrupt, isochronous and bulk transfers * Supports up to 32 endpoints (16 bidirectional) * 256-byte dual access RAM for USB * On-chip USB transceiver with on-chip voltage regulator * Interface for off-chip USB transceiver
Peripheral Highlights:
High-current sink/source: 25 mA/25 mA Three external interrupts Three Timer modules (Timer0 to Timer2) Capture/Compare/PWM (CCP) module: - Capture is 16-bit, max. resolution 5.2 ns - Compare is 16-bit, max. resolution 83.3 ns - PWM output: PWM resolution is 1 to 10-bit * Enhanced USART module: - LIN bus support * 10-bit, up to 13-channel Analog-to-Digital Converter module (A/D): - Up to 100 ksps sampling rate - Programmable acquisition time * * * *
Power-Managed Modes:
* * * * * * * * Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Idle mode currents down to 5.8 A typical Sleep mode currents down to 0.1 A typical Timer1 oscillator: 1.8 A typical, 32 kHz, 2V Watchdog Timer: 2.1 A typical Two-Speed Oscillator Start-up
Special Microcontroller Features:
* C compiler optimized architecture with optional extended instruction set * Flash memory retention: > 40 years * Self-programmable under software control * Priority levels for interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s * Programmable Code Protection * Single-Supply In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * In-Circuit Debug (ICD) via two pins * Optional dedicated ICD/ICSP port (44-pin TQFP devices only) * Wide operating voltage range (2.0V to 5.5V)
Flexible Oscillator Structure:
* Four Crystal modes, including High-Precision PLL for USB * Two External Clock modes, up to 48 MHz * Internal 31 kHz oscillator * Secondary oscillator using Timer1 @ 32 kHz * Dual oscillator options allow microcontroller and USB module to run at different clock speeds * Fail-Safe Clock Monitor: - Allows for safe shutdown if any clock stops
Program Memory Device Flash (bytes) 16K 16K # Single-Word Instructions 8192 8192
Data Memory SRAM (bytes) 768* 768*
I/O
10-Bit A/D (ch) 10 13
CCP
EUSART
Timers 8/16-Bit 1/2 1/2
PIC18F2450 PIC18F4450 *
23 34
1 1
1 1
Includes 256 bytes of dual access RAM used by USB module and shared with data memory.
(c) 2006 Microchip Technology Inc.
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DS39760A-page 1
PIC18F2450/4450
Pin Diagrams
28-Pin SDIP, SOIC
MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI/RCV RA5/AN4/HLVDIN VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/UOE RC2/CCP1 VUSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1 RB0/AN12/INT0 VDD VSS RC7/RX/DT RC6/TX/CK RC5/D+/VP RC4/D-/VM
28-Pin QFN
RA1/AN1 RA0/AN0 MCLR/VPP/RE3 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 28 27 26 25 24 23 22 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI/RCV RA5/AN4/HLVDIN VSS OSC1/CLKI OSC2/CLKO/RA6 1 2 3 4 5 6 7 21 20 19 18 17 16 15 RB3/AN9/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1 RB0/AN12/INT0 VDD VSS RC7/RX/DT
PIC18F2450
8 9 10 11 12 13 14
Note:
Pinouts are subject to change.
DS39760A-page 2
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RC0/T1OSO/T1CKI RC1/T1OSI/UOE RC2/CCP1 VUSB RC4/D-/VM RC5/D+/VP RC6/TX/CK
PIC18F2450
(c) 2006 Microchip Technology Inc.
PIC18F2450/4450
Pin Diagrams (Continued)
40-Pin PDIP
MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI/RCV RA5/AN4/HLVDIN RE0/AN5 RE1/AN6 RE2/AN7 VDD VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/UOE RC2/CCP1 VUSB RD0 RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1 RB0/AN12/INT0 VDD VSS RD7 RD6 RD5 RD4 RC7/RX/DT RC6/TX/CK RC5/D+/VP RC4/D-/VM RD3 RD2
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5/D+/VP RC4/D-/VM RD3 RD2 RD1 RD0 VUSB RC2/CCP1 RC1/T1OSI/UOE RC0/T1OSO/T1CKI
44-Pin QFN
PIC18F4450
Note:
Pinouts are subject to change.
(c) 2006 Microchip Technology Inc.
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RB3/AN9/VPO NC RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4 RD5 RD6 RD7 VSS AVDD VDD RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO
1 2 3 4 5 6 7 8 9 10 11
PIC18F4450
33 32 31 30 29 28 27 26 25 24 23
OSC2/CLKO/RA6 OSC1/CLKI VSS AVSS VDD AVDD RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/HLVDIN RA4/T0CKI/RCV
DS39760A-page 3
PIC18F2450/4450
Pin Diagrams (Continued)
44-Pin TQFP
RC6/TX/CK RC5/D+/VP RC4/D-/VM RD3 RD2 RD1 RD0 VUSB RC2/CCP1 RC1/T1OSI/UOE NC/ICPORTS* 44 43 42 41 40 39 38 37 36 35 34
Note: *
Pinouts are subject to change. Assignment of this feature is dependent on device configuration.
DS39760A-page 4
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NC/ICCK*/ICPGC* NC/ICDT*/ICPGD* RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4 RD5 RD6 RD7 VSS VDD RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO RB3/AN9/VPO
1 2 3 4 5 6 7 8 9 10 11
PIC18F4450
33 32 31 30 29 28 27 26 25 24 23
NC/ICRST*/ICVPP* RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI VSS VDD RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/HLVDIN RA4/T0CKI/RCV
(c) 2006 Microchip Technology Inc.
PIC18F2450/4450
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 23 3.0 Power-Managed Modes ............................................................................................................................................................. 33 4.0 Reset .......................................................................................................................................................................................... 41 5.0 Memory Organization ................................................................................................................................................................. 53 6.0 Flash Program Memory.............................................................................................................................................................. 73 7.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 83 8.0 Interrupts .................................................................................................................................................................................... 85 9.0 I/O Ports ..................................................................................................................................................................................... 99 10.0 Timer0 Module ......................................................................................................................................................................... 111 11.0 Timer1 Module ......................................................................................................................................................................... 115 12.0 Timer2 Module ......................................................................................................................................................................... 121 13.0 Capture/Compare/PWM (CCP) Module ................................................................................................................................... 123 14.0 Universal Serial Bus (USB) ...................................................................................................................................................... 129 15.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 153 16.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 173 17.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 183 18.0 Special Features of the CPU.................................................................................................................................................... 189 19.0 Instruction Set Summary .......................................................................................................................................................... 211 20.0 Development Support............................................................................................................................................................... 261 21.0 Electrical Characteristics .......................................................................................................................................................... 265 22.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 293 23.0 Packaging Information.............................................................................................................................................................. 295 Appendix A: Revision History............................................................................................................................................................. 303 Appendix B: Device Differences ........................................................................................................................................................ 303 Appendix C: Conversion Considerations ........................................................................................................................................... 304 Appendix D: Migration From Baseline to Enhanced Devices ............................................................................................................ 304 Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 305 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 305 Index ................................................................................................................................................................................................. 307 The Microchip Web Site ..................................................................................................................................................................... 315 Customer Change Notification Service .............................................................................................................................................. 315 Customer Support .............................................................................................................................................................................. 315 Reader Response .............................................................................................................................................................................. 316 PIC18F2450/4450 Product Identification System .............................................................................................................................. 317
(c) 2006 Microchip Technology Inc.
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DS39760A-page 5
PIC18F2450/4450
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS39760A-page 6
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(c) 2006 Microchip Technology Inc.
PIC18F2450/4450
1.0 DEVICE OVERVIEW
1.1.3
This document contains device-specific information for the following devices: * PIC18F2450 * PIC18F4450
MULTIPLE OSCILLATOR OPTIONS AND FEATURES
This family of devices offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of high endurance, Enhanced Flash program memory. In addition to these features, the PIC18F2450/4450 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications.
All of the devices in the PIC18F2450/4450 family offer twelve different oscillator options, allowing users a wide range of choices in developing application hardware. These include: * Four Crystal modes using crystals or ceramic resonators. * Four External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O). * An INTRC source (approximately 31 kHz, stable over temperature and VDD). This option frees an oscillator pin for use as an additional general purpose I/O. * A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal and External Oscillator modes, which allows a wide range of clock speeds from 4 MHz to 48 MHz. * Asynchronous dual clock operation, allowing the USB module to run from a high-frequency oscillator while the rest of the microcontroller is clocked from an internal low-power oscillator. The internal oscillator provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.
1.1
1.1.1
New Core Features
nanoWatt TECHNOLOGY
All of the devices in the PIC18F2450/4450 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the Timer1 source or the internal RC oscillator, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. * On-the-Fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate powersaving ideas into their application's software design. * Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 21.0 "Electrical Characteristics" for values.
1.1.2
UNIVERSAL SERIAL BUS (USB)
Devices in the PIC18F2450/4450 family incorporate a fully featured Universal Serial Bus communications module that is compliant with the USB Specification Revision 2.0. The module supports both low-speed and full-speed communication for all supported data transfer types. It also incorporates its own on-chip transceiver and 3.3V regulator and supports the use of external transceivers and voltage regulators.
(c) 2006 Microchip Technology Inc.
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DS39760A-page 7
PIC18F2450/4450
1.2 Other Special Features 1.3
* Memory Endurance: The Enhanced Flash cells for program memory are rated to last for many thousands of erase/write cycles - up to 100,000. * Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine, located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Extended Instruction Set: The PIC18F2450/ 4450 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Literal Offset Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages such as C. * Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include Automatic Baud Rate Detection and a 16-bit Baud Rate Generator for improved resolution. * 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated, without waiting for a sampling period and thus, reducing code overhead. * Dedicated ICD/ICSP Port: These devices introduce the use of debugger and programming pins that are not multiplexed with other microcontroller features. Offered as an option in select packages, this feature allows users to develop I/O intensive applications while retaining the ability to program and debug in the circuit.
Details on Individual Family Members
Devices in the PIC18F2450/4450 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in the following two ways: 1. 2. A/D channels (10 for 28-pin devices, 13 for 40/44-pin devices). I/O ports (3 bidirectional ports and 1 input only port on 28-pin devices, 5 bidirectional ports on 40/44-pin devices).
All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3. Like all Microchip PIC18 devices, members of the PIC18F2450/4450 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an "F" in the part number (such as PIC18F2450), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by "LF" (such as PIC18LF2450), function over an extended VDD range of 2.0V to 5.5V.
DS39760A-page 8
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(c) 2006 Microchip Technology Inc.
PIC18F2450/4450
TABLE 1-1: DEVICE FEATURES
Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Timers Capture/Compare/PWM Modules Enhanced USART Universal Serial Bus (USB) Module 10-bit Analog-to-Digital Module Resets (and Delays) PIC18F2450 DC - 48 MHz 16384 8192 768 13 Ports A, B, C, (E) 3 1 1 1 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions; 83 with Extended Instruction Set enabled 28-pin PDIP 28-pin SOIC PIC18F4450 DC - 48 MHz 16384 8192 768 13 Ports A, B, C, D, E 3 1 1 1 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions; 83 with Extended Instruction Set enabled 40-pin PDIP 44-pin QFN 44-pin TQFP
Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set
Packages
(c) 2006 Microchip Technology Inc.
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DS39760A-page 9
PIC18F2450/4450
FIGURE 1-1: PIC18F2450 (28-PIN) BLOCK DIAGRAM
Data Bus<8> Table Pointer<21> inc/dec logic 21 20 PCU PCH PCL Program Counter 8
PCLATU PCLATH
PORTA 8 Data Latch Data Memory (2 Kbytes) Address Latch 12 Data Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTB RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO RB3/AN9/VPO RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI/RCV RA5/AN4/HLVDIN OSC2/CLKO/RA6
31 Level Stack Address Latch Program Memory (24/32 Kbytes) Data Latch 8
Table Latch
STKPTR
ROM Latch
Instruction Bus <16> IR
Address Decode
8 Instruction Decode & Control State Machine Control Signals PRODH PRODL 3 OSC1(2) OSC2(2) T1OSI T1OSO MCLR(1) VDD, VSS VUSB Single-Supply Programming In-Circuit Debugger Internal Oscillator Block INTRC Oscillator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor Band Gap Reference BITOP 8 8 ALU<8> 8 8 x 8 Multiply 8 W 8 8 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/UOE RC2/CCP1 RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT
8
USB Voltage Regulator
PORTE MCLR/VPP/RE3(1)
BOR HLVD
Timer0
Timer1
Timer2
ADC 10-bit
CCP1
EUSART
USB
Note 1: 2:
RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 "Oscillator Configurations" for additional information.
DS39760A-page 10
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(c) 2006 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 1-2: PIC18F4450 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8> Table Pointer<21> inc/dec logic 21 20 PCU PCH PCL Program Counter 8
PCLATU PCLATH
PORTA Data Latch Data Memory (2 Kbytes) Address Latch 12 Data Address<12> PORTB 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic PORTC RC0/T1OSO/T1CKI RC1/T1OSI/UOE RC2/CCP1 RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT 4 Access Bank 12 RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO RB3/AN9/VPO RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI/RCV RA5/AN4/HLVDIN OSC2/CLKO/RA6
8
31 Level Stack Address Latch Program Memory (24/32 Kbytes) Data Latch 8
Table Latch
STKPTR
ROM Latch
Instruction Bus <16>
IR
Address Decode
8 Instruction Decode & Control State Machine Control Signals PRODH PRODL PORTD VDD, VSS OSC1(2) OSC2(2) T1OSI T1OSO ICPGC(3) ICPGD(3) ICPORTS(3) ICRST(3) MCLR(1) VUSB Internal Oscillator Block INTRC Oscillator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor Band Gap Reference 3 BITOP 8 8 ALU<8> 8 PORTE 8 x 8 Multiply 8 W 8 8
8
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
Single-Supply Programming In-Circuit Debugger
RE0/AN5 RE1/AN6 RE2/AN7 MCLR/VPP/RE3(1)
USB Voltage Regulator
BOR HLVD
Timer0
Timer1
Timer2
CCP1
EUSART
ADC 10-bit
USB
Note 1: 2: 3:
RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 "Oscillator Configurations" for additional information. These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 18.9 "Special ICPORT Features (Designated Packages Only)" for additional information.
(c) 2006 Microchip Technology Inc.
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DS39760A-page 11
PIC18F2450/4450
TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS
Pin Number Pin Name MCLR/Vpp/RE3 MCLR VPP RE3 OSC1/CLKI OSC1 CLKI OSC2/CLKO/RA6 OSC2 CLKO 9 6 I I 10 7 O O -- -- Analog Analog Pin Buffer PDIP, Type Type QFN SOIC 1 26 I P I ST Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power
ST
RA6
I/O
TTL
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
DS39760A-page 12
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(c) 2006 Microchip Technology Inc.
PIC18F2450/4450
TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Name Pin Buffer PDIP, QFN Type Type SOIC 2 27 I/O I 3 28 I/O I 4 1 I/O I I 5 2 I/O I I 6 3 I/O I I 7 4 I/O I I -- -- -- TTL Analog Analog -- Digital I/O. Analog input 4. High/Low-Voltage Detect input. See the OSC2/CLKO/RA6 pin. CMOS = CMOS compatible input or output I = Input P = Power ST ST TTL Digital I/O. Timer0 external clock input. External USB transceiver RCV input. TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. TTL Analog Digital I/O. Analog input 1. TTL Analog Digital I/O. Analog input 0. Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/RCV RA4 T0CKI RCV RA5/AN4/HLVDIN RA5 AN4 HLVDIN RA6
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
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PIC18F2450/4450
TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Name Pin Buffer PDIP, QFN Type Type SOIC Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0 RB0 AN12 INT0 RB1/AN10/INT1 RB1 AN10 INT1 RB2/AN8/INT2/VMO RB2 AN8 INT2 VMO RB3/AN9/VPO RB3 AN9 VPO RB4/AN11/KBI0 RB4 AN11 KBI0 RB5/KBI1/PGM RB5 KBI1 PGM RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD 21 18 I/O I I 22 19 I/O I I 23 20 I/O I I O 24 21 I/O I O 25 22 I/O I I 26 23 I/O I I/O 27 24 I/O I I/O 28 25 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSPTM Programming enable pin. TTL Analog TTL Digital I/O. Analog input 11. Interrupt-on-change pin. TTL Analog -- Digital I/O. Analog input 9. External USB transceiver VPO output. TTL Analog ST -- Digital I/O. Analog input 8. External interrupt 2. External USB transceiver VMO output. TTL Analog ST Digital I/O. Analog input 10. External interrupt 1. TTL Analog ST Digital I/O. Analog input 12. External interrupt 0.
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
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PIC18F2450/4450
TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Name Pin Buffer PDIP, QFN Type Type SOIC 11 8 I/O O I 12 9 I/O I -- 13 10 I/O I/O 15 12 I I/O I 16 13 I I/O O 17 14 I/O O I/O 18 15 I/O I I/O -- 14 20 -- 11 17 -- O P P ST ST ST -- -- -- -- Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see TX/CK). See MCLR/VPP/RE3 pin. Internal USB 3.3V voltage regulator. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output I = Input P = Power ST -- ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see RX/DT). TTL -- TTL Digital input. USB differential plus line (input/output). External USB transceiver VP input. TTL -- TTL Digital input. USB differential minus line (input/output). External USB transceiver VM input. ST ST Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output. ST CMOS -- Digital I/O. Timer1 oscillator input. External USB transceiver OE output. ST -- ST Digital I/O. Timer1 oscillator output. Timer1external clock input. Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/UOE RC1 T1OSI UOE RC2/CCP1 RC2 CCP1 RC4/D-/VM RC4 DVM RC5/D+/VP RC5 D+ VP RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT RE3 VUSB VSS VDD
8, 19 5, 16
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
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PIC18F2450/4450
TABLE 1-3:
Pin Name MCLR/Vpp/RE3 MCLR VPP RE3 OSC1/CLKI OSC1 CLKI OSC2/CLKO/RA6 OSC2 CLKO 13 32 30 I I 14 33 31 O O -- -- Analog Analog
PIC18F4450 PINOUT I/O DESCRIPTIONS
Pin Number PDIP 1 QFN 18 Pin Buffer TQFP Type Type 18 I P I ST Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.
ST
RA6
I/O
TTL
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39760A-page 16
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PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP 2 QFN 19 Pin Buffer TQFP Type Type 19 I/O I 3 20 20 I/O I 4 21 21 I/O I I 5 22 22 I/O I I 6 23 23 I/O I I 7 24 24 I/O I I -- -- -- -- TTL Analog Analog -- Digital I/O. Analog input 4. High/Low-Voltage Detect input. See the OSC2/CLKO/RA6 pin. ST ST TTL Digital I/O. Timer0 external clock input. External USB transceiver RCV input. TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. TTL Analog Digital I/O. Analog input 1. TTL Analog Digital I/O. Analog input 0. Description PORTA is a bidirectional I/O port.
RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/RCV RA4 T0CKI RCV RA5/AN4/HLVDIN RA5 AN4 HLVDIN RA6
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
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PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0 RB0 AN12 INT0 RB1/AN10/INT1 RB1 AN10 INT1 RB2/AN8/INT2/VMO RB2 AN8 INT2 VMO RB3/AN9/VPO RB3 AN9 VPO RB4/AN11/KBI0 RB4 AN11 KBI0 RB5/KBI1/PGM RB5 KBI1 PGM RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD
33
9
8 I/O I I TTL Analog ST TTL Analog ST TTL Analog ST -- TTL Analog -- TTL Analog TTL TTL TTL ST TTL TTL ST TTL TTL ST Digital I/O. Analog input 12. External interrupt 0. Digital I/O. Analog input 10. External interrupt 1. Digital I/O. Analog input 8. External interrupt 2. External USB transceiver VMO output. Digital I/O. Analog input 9. External USB transceiver VPO output. Digital I/O. Analog input 11. Interrupt-on-change pin. Digital I/O. Interrupt-on-change pin. Low-Voltage ICSPTM Programming enable pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.
34
10
9 I/O I I
35
11
10 I/O I I O
36
12
11 I/O I O
37
14
14 I/O I I
38
15
15 I/O I I/O
39
16
16 I/O I I/O
40
17
17 I/O I I/O
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39760A-page 18
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PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP 15 QFN 34 Pin Buffer TQFP Type Type 32 I/O O I 16 35 35 I/O I O 17 36 36 I/O I/O 23 42 42 I I/O I 24 43 43 I I/O I 25 44 44 I/O O I/O 26 1 1 I/O I I/O ST ST ST Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see TX/CK). ST -- ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see RX/DT). TTL -- TTL Digital input. USB differential plus line (input/output). External USB transceiver VP input. TTL -- TTL Digital input. USB differential minus line (input/output). External USB transceiver VM input. ST ST Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output. ST CMOS -- Digital I/O. Timer1 oscillator input. External USB transceiver OE output. ST -- ST Digital I/O. Timer1 oscillator output. Timer1 external clock input. Description PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/UOE RC1 T1OSI UOE RC2/CCP1 RC2 CCP1 RC4/D-/VM RC4 DVM RC5/D+/VP RC5 D+ VP RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
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PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTD is a bidirectional I/O port.
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
19 20 21 22 27 28 29 30
38 39 40 41 2 3 4 5
38 39 40 41 2 3 4 5
I/O I/O I/O I/O I/O I/O I/O I/O
ST ST ST ST ST ST ST ST
Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39760A-page 20
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PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP 8 QFN 25 Pin Buffer TQFP Type Type 25 I/O I 9 26 26 I/O I 10 27 27 I/O I -- -- -- 6, 29 -- P P O I/O I/O -- -- 13 I/O I/O -- -- 33 I P -- -- 34 P -- -- -- ST ST 12, 31 6, 30, 31 ST Analog -- -- -- -- ST ST Digital I/O. Analog input 7. See MCLR/VPP/RE3 pin. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. Internal USB 3.3V voltage regulator output. No Connect or dedicated ICD/ICSPTM port clock. In-Circuit Debugger clock. ICSP programming clock. No Connect or dedicated ICD/ICSP port clock. In-Circuit Debugger data. ICSP programming data. No Connect or dedicated ICD/ICSP port Reset. Master Clear (Reset) input. Programming voltage input. No Connect or 28-pin device emulation. Enable 28-pin device emulation when connected to VSS. No Connect. ST Analog Digital I/O. Analog input 6. ST Analog Digital I/O. Analog input 5. Description PORTE is a bidirectional I/O port.
RE0/AN5 RE0 AN5 RE1/AN6 RE1 AN6 RE2/AN7 RE2 AN7 RE3 VSS VDD VUSB NC/ICCK/ICPGC ICCK ICPGC
(1)
11, 32 7, 8, 7, 28 28, 29 18 -- 37 -- 37 12
NC/ICDT/ICPGD(1) ICDT ICPGD NC/ICRST/ICVPP(1) ICRST ICVPP NC/ICPORTS(1) ICPORTS NC
--
13
--
--
--
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
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PIC18F2450/4450
NOTES:
DS39760A-page 22
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PIC18F2450/4450
2.0
2.1
OSCILLATOR CONFIGURATIONS
Overview
2.2
Oscillator Types
Devices in the PIC18F2450/4450 family incorporate a different oscillator and microcontroller clock system than the non-USB PIC18F devices. The addition of the USB module, with its unique requirements for a stable clock source, make it necessary to provide a separate clock source that is compliant with both USB low-speed and full-speed specifications. To accommodate these requirements, PIC18F2450/ 4450 devices include a new clock branch to provide a 48 MHz clock for full-speed USB operation. Since it is driven from the primary clock source, an additional system of prescalers and postscalers has been added to accommodate a wide range of oscillator frequencies. An overview of the oscillator structure is shown in Figure 2-1. Other oscillator features used in PIC18 enhanced microcontrollers, such as the internal RC oscillator and clock switching, remain the same. They are discussed later in this chapter.
PIC18F2450/4450 devices can be operated in twelve distinct oscillator modes. In contrast with the non-USB PIC18 enhanced microcontrollers, four of these modes involve the use of two oscillator types at once. Users can program the FOSC3:FOSC0 Configuration bits to select one of these modes: Crystal/Resonator Crystal/Resonator with PLL enabled High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL enabled 5. EC External Clock with FOSC/4 output 6. ECIO External Clock with I/O on RA6 7. ECPLL External Clock with PLL enabled and FOSC/4 output on RA6 8. ECPIO External Clock with PLL enabled, I/O on RA6 9. INTHS Internal Oscillator used as microcontroller clock source, HS Oscillator used as USB clock source 10. INTXT Internal Oscillator used as microcontroller clock source, XT Oscillator used as USB clock source 11. INTIO Internal Oscillator used as microcontroller clock source, EC Oscillator used as USB clock source, digital I/O on RA6 12. INTCKO Internal Oscillator used as microcontroller clock source, EC Oscillator used as USB clock source, FOSC/4 output on RA6 1. 2. 3. 4. XT XTPLL HS HSPLL
2.1.1
OSCILLATOR CONTROL
The operation of the oscillator in PIC18F2450/4450 devices is controlled through two Configuration registers and two control registers. Configuration registers, CONFIG1L and CONFIG1H, select the oscillator mode and USB prescaler/postscaler options. As Configuration bits, these are set when the device is programmed and left in that configuration until the device is reprogrammed. The OSCCON register (Register 2-1) selects the Active Clock mode; it is primarily used in controlling clock switching in power-managed modes. Its use is discussed in Section 2.4.1 "Oscillator Control Register".
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PIC18F2450/4450
2.2.1 OSCILLATOR MODES AND USB OPERATION
Because of the unique requirements of the USB module, a different approach to clock operation is necessary. In previous PICmicro(R) devices, all core and peripheral clocks were driven by a single oscillator source; the usual sources were primary, secondary or the internal oscillator. With PIC18F2450/4450 devices, the primary oscillator becomes part of the USB module and cannot be associated to any other clock source. Thus, the USB module must be clocked from the primary clock source; however, the microcontroller core and other peripherals can be separately clocked from the secondary or internal oscillators as before. Because of the timing requirements imposed by USB, an internal clock of either 6 MHz or 48 MHz is required while the USB module is enabled. Fortunately, the microcontroller and other peripherals are not required to run at this clock speed when using the primary oscillator. There are numerous options to achieve the USB module clock requirement and still provide flexibility for clocking the rest of the device from the primary oscillator source. These are detailed in Section 2.3 "Oscillator Settings for USB".
FIGURE 2-1:
PIC18F2450/4450 CLOCK DIAGRAM
PIC18F2450/4450
PLLDIV / 12 / 10 PLL Prescaler /6 /5 /4 /3 /2 /1 111 110 101 MUX 100 011 010 001 000 HSPLL, ECPLL, XTPLL, ECPIO CPUDIV PLL Postscaler /6 /4 /3 /2 11 10 01 00 CPU Primary Clock FOSC3:FOSC0 T1OSC T1OSCEN Enable Oscillator OSCCON<6:4> Internal Oscillator MUX 1 0 /4 0 1 USB Peripheral FSEN (4 MHz Input Only) 96 MHz PLL /2 USBDIV 0 1
USB Clock Source
Primary Oscillator OSC2 Sleep OSC1
CPUDIV Oscillator Postscaler /4 /3 /2 /1 11 10 01 00
XT, HS, EC, ECIO
IDLEN Peripherals
Secondary Oscillator T1OSO
T1OSI
Internal RC Oscillator 31.25 kHz
Clock Control FOSC3:FOSC0 OSCCON<1:0>
Clock Source Option for other Modules
WDT, PWRT, FSCM and Two-Speed Start-up
DS39760A-page 24
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PIC18F2450/4450
2.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Crystal Freq 4 MHz 4 MHz 8 MHz 20 MHz Typical Capacitor Values Tested: C1 XT HS 27 pF 27 pF 22 pF 15 pF C2 27 pF 27 pF 22 pF 15 pF In HS, HSPLL, XT and XTPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-2 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications.
Osc Type
Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 4 MHz 8 MHz 20 MHz Note 1: Higher capacitance increases the stability of oscillator but also increases the startup time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application. An internal postscaler allows users to select a clock frequency other than that of the crystal or resonator. Frequency division is determined by the CPUDIV Configuration bits. Users may select a clock frequency of the oscillator frequency, or 1/2, 1/3 or 1/4 of the frequency. An external clock may also be used when the microcontroller is in HS Oscillator mode. In this case, the OSC2/CLKO pin is left open (Figure 2-3).
FIGURE 2-2:
CRYSTAL/CERAMIC RESONATOR OPERATION (XT, HS OR HSPLL CONFIGURATION)
OSC1 To Internal Logic Sleep
C1(1)
XTAL
RS(2) C2(1) OSC2
RF(3)
PIC18FXXXX
Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen.
TABLE 2-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS
Typical Capacitor Values Used: Mode XT HS Freq 4.0 MHz 8.0 MHz 16.0 MHz OSC1 33 pF 27 pF 22 pF OSC2 33 pF 27 pF 22 pF
Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 2-2 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz
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PIC18F2450/4450
FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION)
OSC1
2.2.4
PLL FREQUENCY MULTIPLIER
Clock from Ext. System Open
PIC18F2450/4450 devices include a Phase Locked Loop (PLL) circuit. This is provided specifically for USB applications with lower speed oscillators and can also be used as a microcontroller clock source. The PLL is enabled in HSPLL, XTPLL, ECPLL and ECPIO Oscillator modes. It is designed to produce a fixed 96 MHz reference clock from a fixed 4 MHz input. The output can then be divided and used for both the USB and the microcontroller core clock. Because the PLL has a fixed frequency input and output, there are eight prescaling options to match the oscillator input frequency to the PLL. There is also a separate postscaler option for deriving the microcontroller clock from the PLL. This allows the USB peripheral and microcontroller to use the same oscillator input and still operate at different clock speeds. In contrast to the postscaler for XT, HS and EC modes, the available options are 1/2, 1/3, 1/4 and 1/6 of the PLL output. The HSPLL, ECPLL and ECPIO modes make use of the HS mode oscillator for frequencies up to 48 MHz. The prescaler divides the oscillator input by up to 12 to produce the 4 MHz drive for the PLL. The XTPLL mode can only use an input frequency of 4 MHz which drives the PLL directly.
PIC18FXXXX
OSC2 (HS Mode)
2.2.3
EXTERNAL CLOCK INPUT
The EC, ECIO, ECPLL and ECPIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC and ECPLL Oscillator modes, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT OPERATION (EC AND ECPLL CONFIGURATION)
OSC1/CLKI
Clock from Ext. System FOSC/4
FIGURE 2-6:
PIC18FXXXX
OSC2/CLKO
PLL BLOCK DIAGRAM (HS MODE)
HS/EC/ECIO/XT Oscillator Enable PLL Enable (from CONFIG1H Register) OSC2
Oscillator and OSC1 Prescaler
The ECIO and ECPIO Oscillator modes function like the EC and ECPLL modes, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode.
FIN FOUT
Phase Comparator
FIGURE 2-5:
EXTERNAL CLOCK INPUT OPERATION (ECIO AND ECPIO CONFIGURATION)
/24 OSC1/CLKI
Loop Filter
VCO MUX
SYSCLK
Clock from Ext. System RA6
PIC18FXXXX
I/O (OSC2)
The internal postscaler for reducing clock frequency in XT and HS modes is also available in EC and ECIO modes.
DS39760A-page 26
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PIC18F2450/4450
2.2.5 INTERNAL OSCILLATOR
2.3
Oscillator Settings for USB
The PIC18F2450/4450 devices include an internal RC oscillator (INTRC) which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled: * * * * Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up
When the PIC18F2450/4450 is used for USB connectivity, it must have either a 6 MHz or 48 MHz clock for USB operation, depending on whether LowSpeed or Full-Speed mode is being used. This may require some forethought in selecting an oscillator frequency and programming the device. The full range of possible oscillator configurations compatible with USB operation is shown in Table 2-3.
2.3.1
LOW-SPEED OPERATION
These features are discussed in greater detail in Section 18.0 "Special Features of the CPU".
2.2.5.1
Internal Oscillator Modes
When the internal oscillator is used as the microcontroller clock source, one of the other oscillator modes (External Clock or External Crystal/Resonator) must be used as the USB clock source. The choice of USB clock source is determined by the particular internal oscillator mode. There are four distinct modes available: 1. 2. 3. INTHS mode: The USB clock is provided by the oscillator in HS mode. INTXT mode: The USB clock is provided by the oscillator in XT mode. INTCKO mode: The USB clock is provided by an external clock input on OSC1/CLKI; the OSC2/ CLKO pin outputs FOSC/4. INTIO mode: The USB clock is provided by an external clock input on OSC1/CLKI; the OSC2/ CLKO pin functions as a digital I/O (RA6).
The USB clock for Low-Speed mode is derived from the primary oscillator chain and not directly from the PLL. It is divided by 4 to produce the actual 6 MHz clock. Because of this, the microcontroller can only use a clock frequency of 24 MHz when the USB module is active and the controller clock source is one of the primary oscillator modes (XT, HS or EC, with or without the PLL). This restriction does not apply if the microcontroller clock source is the secondary oscillator or internal oscillator.
2.3.2
RUNNING DIFFERENT USB AND MICROCONTROLLER CLOCKS
4.
Of these four modes, only INTIO mode frees up an additional pin (OSC2/CLKO/RA6) for port I/O use.
The USB module, in either mode, can run asynchronously with respect to the microcontroller core and other peripherals. This means that applications can use the primary oscillator for the USB clock while the microcontroller runs from a separate clock source at a lower speed. If it is necessary to run the entire application from only one clock source, full-speed operation provides a greater selection of microcontroller clock frequencies.
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PIC18F2450/4450
TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION
PLL Division (PLLDIV2:PLLDIV0) N/A(1) Clock Mode (FOSC3:FOSC0) EC, ECIO MCU Clock Division (CPUDIV1:CPUDIV0) None (00) /2 (01) /3 (10) /4 (11) 48 MHz /12 (111) EC, ECIO None (00) /2 (01) /3 (10) /4 (11) ECPLL, ECPIO /2 (00) /3 (01) /4 (10) /6 (11) 40 MHz /10 (110) EC, ECIO None (00) /2 (01) /3 (10) /4 (11) ECPLL, ECPIO /2 (00) /3 (01) /4 (10) /6 (11) 24 MHz /6 (101) HS, EC, ECIO None (00) /2 (01) /3 (10) /4 (11) HSPLL, ECPLL, ECPIO /2 (00) /3 (01) /4 (10) /6 (11) 20 MHz /5 (100) HS, EC, ECIO None (00) /2 (01) /3 (10) /4 (11) HSPLL, ECPLL, ECPIO /2 (00) /3 (01) /4 (10) /6 (11) 16 MHz /4 (011) HS, EC, ECIO None (00) /2 (01) /3 (10) /4 (11) HSPLL, ECPLL, ECPIO /2 (00) /3 (01) /4 (10) /6 (11) Legend: Microcontroller Clock Frequency 48 MHz 24 MHz 16 MHz 12 MHz 48 MHz 24 MHz 16 MHz 12 MHz 48 MHz 32 MHz 24 MHz 16 MHz 40 MHz 20 MHz 13.33 MHz 10 MHz 48 MHz 32 MHz 24 MHz 16 MHz 24 MHz 12 MHz 8 MHz 6 MHz 48 MHz 32 MHz 24 MHz 16 MHz 20 MHz 10 MHz 6.67 MHz 5 MHz 48 MHz 32 MHz 24 MHz 16 MHz 16 MHz 8 MHz 5.33 MHz 4 MHz 48 MHz 32 MHz 24 MHz 16 MHz Input Oscillator Frequency 48 MHz
Note 1:
All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). Only valid when the USBDIV Configuration bit is cleared.
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TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)
PLL Division (PLLDIV2:PLLDIV0) /3 (010) Clock Mode (FOSC3:FOSC0) HS, EC, ECIO MCU Clock Division (CPUDIV1:CPUDIV0) None (00) /2 (01) /3 (10) /4 (11) HSPLL, ECPLL, ECPIO /2 (00) /3 (01) /4 (10) /6 (11) 8 MHz /2 (001) HS, EC, ECIO None (00) /2 (01) /3 (10) /4 (11) HSPLL, ECPLL, ECPIO /2 (00) /3 (01) /4 (10) /6 (11) 4 MHz /1 (000) XT, HS, EC, ECIO None (00) /2 (01) /3 (10) /4 (11) HSPLL, ECPLL, XTPLL, ECPIO /2 (00) /3 (01) /4 (10) /6 (11) Legend: Microcontroller Clock Frequency 12 MHz 6 MHz 4 MHz 3 MHz 48 MHz 32 MHz 24 MHz 16 MHz 8 MHz 4 MHz 2.67 MHz 2 MHz 48 MHz 32 MHz 24 MHz 16 MHz 4 MHz 2 MHz 1.33 MHz 1 MHz 48 MHz 32 MHz 24 MHz 16 MHz Input Oscillator Frequency 12 MHz
Note 1:
All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). Only valid when the USBDIV Configuration bit is cleared.
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2.4 Clock Sources and Oscillator Switching
INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor. The OSTS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the device clock in primary clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode, or one of the Idle modes, when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0 "Power-Managed Modes". Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable prior to switching to it as the clock source; otherwise, a very long delay may occur while the Timer1 oscillator starts.
Like previous PIC18 enhanced devices, the PIC18F2450/4450 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2450/4450 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator The primary oscillators include the External Crystal and Resonator modes, the External Clock modes and the internal oscillator. The particular mode is defined by the FOSC3:FOSC0 Configuration bits. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F2450/4450 devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all powermanaged modes, is often the time base for functions such as a Real-Time Clock. Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/ T1CKI and RC1/T1OSI/UOE pins. Like the XT and HS Oscillator mode circuits, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 11.3 "Timer1 Oscillator". In addition to being a primary clock source, the internal oscillator is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor.
2.4.2
OSCILLATOR TRANSITIONS
2.4.1
OSCILLATOR CONTROL REGISTER
PIC18F2450/4450 devices contain circuitry to prevent clock "glitches" when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 "Entering Power-Managed Modes".
The OSCCON register (Register 2-1) controls several aspects of the device clock's operation, both in full power operation and in power-managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator. The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared on all forms of Reset.
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REGISTER 2-1:
R/W-0 IDLEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OSCCON: OSCILLATOR CONTROL REGISTER
U-0 -- U-0 -- U-0 -- R(1) OSTS U-0 -- R/W-0 SCS1 R/W-0 SCS0 bit 0
IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction Unimplemented: Read as `0' OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready Unimplemented: Read as `0' SCS1:SCS0: System Clock Select bits 1x = Internal oscillator 01 = Timer1 oscillator 00 = Primary oscillator Depends on the state of the IESO Configuration bit.
bit 6-4 bit 3
bit 2 bit 1-0
Note 1:
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2.5 Effects of Power-Managed Modes on the Various Clock Sources
Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a RealTime Clock. Other features may be operating that do not require a device clock source (i.e., PSP, INTn pins and others). Peripherals that may add significant current consumption are listed in Section 21.2 "DC Characteristics: Power-Down and Supply Current".
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. Unless the USB module is enabled, the OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features regardless of the power-managed mode (see Section 18.2 "Watchdog Timer (WDT)", Section 18.3 "Two-Speed Start-up" and Section 18.4 "Fail-Safe Clock Monitor" for more information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up). Regardless of the Run or Idle mode selected, the USB clock source will continue to operate. If the device is operating from a crystal or resonator-based oscillator, that oscillator will continue to clock the USB module. The core and all other modules will switch to the new clock source. If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Sleep mode should never be invoked while the USB module is operating and connected. The only exception is when the device has been issued a "Suspend" command over the USB. Once the module has suspended operation and shifted to a low-power state, the microcontroller may be safely put into Sleep mode.
2.6
Power-up Delays
Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.5 "Device Reset Timers". The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 21-10). It is enabled by clearing (= 0) the PWRTEN Configuration bit. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of interval, TCSD (parameter 38, Table 21-10), following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC or internal oscillator modes are used as the primary clock source.
TABLE 2-4:
INTCKO INTIO ECIO, ECPIO EC XT and HS Note:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin Floating, pulled by external clock Floating, pulled by external clock Floating, pulled by external clock Floating, pulled by external clock Feedback inverter disabled at quiescent voltage level OSC2 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level
Oscillator Mode
See Table 4-2 in Section 4.0 "Reset" for time-outs due to Sleep and MCLR Reset.
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3.0 POWER-MANAGED MODES
3.1.1 CLOCK SOURCES
PIC18F2450/4450 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: * Run modes * Idle modes * Sleep mode These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator); the Sleep mode does not use a clock source. The power-managed modes include several powersaving features offered on previous PICmicro(R) devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PICmicro devices, where all device clocks are stopped. The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: * The primary clock, as defined by the FOSC3:FOSC0 Configuration bits * The secondary clock (the Timer1 oscillator) * The internal oscillator (for RC modes)
3.1.2
ENTERING POWER-MANAGED MODES
Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS1:SCS0 bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 3.1.3 "Clock Transitions and Status Indicators" and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode.
3.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS1:SCS0 bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1.
TABLE 3-1:
Mode Sleep PRI_RUN SEC_RUN RC_RUN PRI_IDLE SEC_IDLE RC_IDLE Note 1: 2:
POWER-MANAGED MODES
OSCCON Bits IDLEN(1) 0 N/A N/A N/A 1 1 1 SCS1:SCS0 N/A 00 01 1x 00 01 1x Module Clocking Available Clock and Oscillator Source CPU Off Clocked Clocked Clocked Off Off Off Peripherals Off Clocked Clocked Clocked Clocked Clocked Clocked None - all clocks are disabled Primary - all oscillator modes. This is the normal full power execution mode. Secondary - Timer1 oscillator Internal oscillator(2) Primary - all oscillator modes Secondary - Timer1 oscillator Internal oscillator(2)
IDLEN reflects its value when the SLEEP instruction is executed. Clock is INTRC source.
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3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS 3.2.1 PRI_RUN MODE
The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status. They are: * OSTS (OSCCON<3>) * T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. Note: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode, or one of the Idle modes, depending on the setting of the IDLEN bit. The PRI_RUN mode is the normal, full power execution mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section 18.3 "Two-Speed Start-up" for details). In this mode, the OSTS bit is set.
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. SEC_RUN mode is entered by setting the SCS1:SCS0 bits to `01'. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS1:SCS0 bits are set to `01', entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.
3.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting.
3.2
Run Modes
In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source.
On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 1 2 3 n-1
(1)
Q3
Q4
Q1
Q2
Q3
T1OSI OSC1 CPU Clock Peripheral Clock Program Counter Note 1: PC
n
Clock Transition
PC + 2
PC + 4
Clock transition typically occurs within 2-4 TOSC.
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FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 T1OSI OSC1 TOST(1) PLL Clock Output TPLL(1) 1 2 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
Clock(2) Transition CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed Note 1: 2: PC OSTS bit Set PC + 2 PC + 4
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Clock transition typically occurs within 2-4 TOSC.
3.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator (INTRC), there are no distinguishable differences between the PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator, the use of RC_RUN mode is not recommended.
This mode is entered by setting SCS1 to `1'. Although it is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to the INTRC (see Figure 3-3), the primary oscillator is shut down and the OSTS bit is cleared. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.
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FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1 INTRC OSC1 CPU Clock Peripheral Clock Program Counter Note 1: PC Clock transition typically occurs within 2-4 TOSC. PC + 2 PC + 4 1 2 3 n-1 n Q2 Q3 Q4 Q1 Q2 Q3
Clock Transition(1)
FIGURE 3-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
PLL Clock Output
Clock(2) Transition CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed Note 1: 2: PC OSTS bit Set PC + 2 PC + 4
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Clock transition typically occurs within 2-4 TOSC.
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3.3 Sleep Mode 3.4 Idle Modes
The power-managed Sleep mode in the PIC18F2450/ 4450 devices is identical to the legacy Sleep mode offered in all other PICmicro devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS1:SCS0 bits becomes ready (see Figure 3-6), or it will be clocked from the internal oscillator if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 18.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 21-10) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits.
FIGURE 3-5:
OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
PC + 2
FIGURE 3-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 PLL Clock Output CPU Clock Peripheral Clock Program Counter Wake Event PC OSTS bit Set PC + 2 PC + 4 PC + 6 TOST(1) TPLL(1)
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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3.4.1 PRI_IDLE MODE 3.4.2 SEC_IDLE MODE
This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation, with its more accurate primary clock source, since the clock source does not have to "warm up" or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC3:FOSC0 Configuration bits. The OSTS bit remains set (see Figure 3-7). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval TCSD is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-8). In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS1:SCS0 to `01' and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 3-8). Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.
FIGURE 3-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1 Q2 Q3 Q4 Q1
OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2
FIGURE 3-8:
Q1 OSC1
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q2 Q3 Q4
TCSD CPU Clock Peripheral Clock Program Counter Wake Event PC
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3.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator, INTRC. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. Although its value is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to the INTRC, the primary oscillator is shut down and the OSTS bit is cleared. When a wake event occurs, the peripherals continue to be clocked from the INTRC. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the INTRC. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. A fixed delay of interval TCSD, following the wake event, is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.
3.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 3.2 "Run Modes" and Section 3.3 "Sleep Mode"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 18.2 "Watchdog Timer (WDT)").
3.5.3
EXIT BY RESET
3.5
Exiting Idle and Sleep Modes
Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready. At that time, the OSTS bit is set and the device begins executing code. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are summarized in Table 3-2. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 18.3 "Two-Speed Start-up") or Fail-Safe Clock Monitor (see Section 18.4 "Fail-Safe Clock Monitor") is enabled, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTRC driven by the internal oscillator. Execution is clocked by the internal oscillator until either the primary clock becomes ready or a powermanaged mode is entered before the primary clock becomes ready; the primary clock is then shut down.
An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 3.2 "Run Modes", Section 3.3 "Sleep Mode" and Section 3.4 "Idle Modes").
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the device to exit from an Idle mode, or the Sleep mode, to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 8.0 "Interrupts").
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3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY
Certain exits from power-managed modes do not invoke the OST at all. There are two cases: * PRI_IDLE mode, where the primary clock source is not stopped; and * the primary clock source is not any of the XT or HS modes. In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (EC and any internal oscillator modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.
TABLE 3-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES)
Microcontroller Clock Source Exit Delay Clock Ready Status Bit (OSCCON)
Before Wake-up
After Wake-up XT, HS
Primary Device Clock (PRI_IDLE mode)
XTPLL, HSPLL EC INTRC(1) XT, HS
None
OSTS
TOST(3) TOST + trc(3) TCSD(2) TIOBST(4) TOST(3) TOST + trc(3) TCSD(2) None TOST(3) TOST + trc(3) TCSD(2) TIOBST(4) OSTS OSTS OSTS
T1OSC or INTRC(1)
XTPLL, HSPLL EC INTRC(1) XT, HS XTPLL, HSPLL EC INTRC(1) XT, HS
INTRC(1)
None (Sleep mode) Note 1: 2: 3: 4:
XTPLL, HSPLL EC INTRC(1)
In this instance, refers specifically to the 31 kHz INTRC clock source. TCSD (parameter 38, Table 21-10) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section 3.4 "Idle Modes"). TOST is the Oscillator Start-up Timer period (parameter 32, Table 21-10). trc is the PLL lock time-out (parameter F12, Table 21-7); it is also designated as TPLL. Execution continues during TIOBST (parameter 39, Table 21-10), the INTRC stabilization period.
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4.0 RESET
A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. The PIC18F2450/4450 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset
4.1
RCON Register
Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.6 "Reset State of Registers". The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 8.0 "Interrupts". BOR is covered in Section 4.4 "Brown-out Reset (BOR)".
This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.1.2.4 "Stack Full and Underflow Resets". WDT Resets are covered in Section 18.2 "Watchdog Timer (WDT)".
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Stack Pointer
Stack Full/Underflow Reset
External Reset MCLR MCLRE ( )_IDLE Sleep WDT Time-out VDD Rise Detect VDD Brown-out Reset BOREN OST/PWRT OST OSC1 32 s INTRC(1) 1024 Cycles R Q 10-bit Ripple Counter Chip_Reset S POR Pulse
PWRT
65.5 ms
11-bit Ripple Counter
Enable PWRT Enable OST(2) Note 1: 2: This is the INTRC source from the internal oscillator and is separate from the RC oscillator of the CLKI pin. See Table 4-2 for time-out situations.
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REGISTER 4-1:
R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCON: RESET CONTROL REGISTER
R/W-1(1) SBOREN U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0(2) POR R/W-0 BOR bit 0
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) SBOREN: BOR Software Enable bit(1) If BOREN1:BOREN0 = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00, 10 or 11: Bit is disabled and read as `0'. Unimplemented: Read as `0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) If SBOREN is enabled, its Reset state is `1'; otherwise, it is `0'. The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 4.6 "Reset State of Registers" for additional information.
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is `0' and POR is `1' (assuming that POR was set to `1' by software immediately after POR).
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4.2 Master Clear Reset (MCLR)
FIGURE 4-2:
The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2450/4450 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 9.5 "PORTE, TRISE and LATE Registers" for more information.
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
VDD D
R R1 MCLR C
PIC18FXXXX
Note 1:
4.3
Power-on Reset (POR)
2:
A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004, Section267 "DC Characteristics"). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to `0' whenever a POR occurs; it does not change for any other Reset event. POR is not reset to `1' by any hardware event. To capture multiple events, the user manually resets the bit to `1' in software following any POR.
External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. R1 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
3:
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4.4 Brown-out Reset (BOR)
PIC18F2450/4450 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any values of BOREN1:BOREN0 except `00'), any drop of VDD below VBOR (parameter D005, Section 267 "DC Characteristics: Supply Voltage") for greater than TBOR (parameter 35, Table 21-10) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT (parameter 33, Table 21-10). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. BOR and the Power-on Timer (PWRT) are independently configured. Enabling BOR Reset does not automatically enable the PWRT. Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. Note: Even when BOR is under software control, the BOR Reset voltage level is still set by the BORV1:BORV0 Configuration bits. It cannot be changed in software.
4.4.2
DETECTING BOR
When BOR is enabled, the BOR bit always resets to `0' on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to `1' in software immediately after any POR event. IF BOR is `0' while POR is `1', it can be reliably assumed that a BOR event has occurred.
4.4.3
DISABLING BOR IN SLEEP MODE
4.4.1
SOFTWARE ENABLED BOR
When BOREN1:BOREN0 = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<6>). Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise, it is read as `0'.
When BOREN1:BOREN0 = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current.
TABLE 4-1:
BOR CONFIGURATIONS
Status of SBOREN (RCON<6>) Unavailable Available Unavailable Unavailable BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits.
BOR Configuration BOREN1 0 0 1 1 BOREN0 0 1 0 1
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4.5 Device Reset Timers
4.5.3 PLL LOCK TIME-OUT
PIC18F2450/4450 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: * Power-up Timer (PWRT) * Oscillator Start-up Timer (OST) * PLL Lock Time-out With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out.
4.5.4
1. 2.
TIME-OUT SEQUENCE
4.5.1
POWER-UP TIMER (PWRT)
On power-up, the time-out sequence is as follows: After the POR condition has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated.
The Power-up Timer (PWRT) of the PIC18F2450/4450 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation. See DC parameter 33 (Table 21-10) for details. The PWRT is enabled by clearing the PWRTEN Configuration bit.
The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figure 4-3 through Figure 4-6 also apply to devices operating in XT mode. For devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel.
4.5.2
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33, Table 21-10). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, HS and HSPLL modes and only on Power-on Reset or on exit from most power-managed modes.
TABLE 4-2:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out PWRTEN = 0 66 66 ms(1) + 1024 TOSC ms(2) ms(1) + 2 ms
(2)
Oscillator Configuration HS, XT HSPLL, XTPLL EC, ECIO ECPLL, ECPIO INTIO, INTCKO INTHS, INTXT Note 1: 2: 66
PWRTEN = 1 1024 TOSC 1024 TOSC + 2 -- 2 ms -- 1024 TOSC
(2)
Exit from Power-Managed Mode 1024 TOSC 1024 TOSC + 2 ms(2) -- 2 ms(2) -- 1024 TOSC
ms(1)
+ 1024 TOSC + 2 66
(1)
ms(2)
66 ms
66 ms(1) ms(1) + 1024 TOSC
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2 ms is the nominal time required for the PLL to lock.
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FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
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FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 0V 1V
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST TPLL
OST TIME-OUT
PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the Power-up Timer.
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4.6 Reset State of Registers
Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state" depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations as indicated in Table 4-3. These bits are used in software to determine the nature of the Reset. Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER
Condition Program Counter 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h PC + 2 PC + 2(1) RCON Register SBOREN 1 u(2) u
(2)
STKPTR Register POR BOR STKFUL STKUNF 0 u u u u u u u u u u u 0 u 0 u u u u u u u u u 0 u u u u u u 1 u u u u 0 u u u u u u u 1 1 u u
RI 1 0 1 u u u u u u u u u
TO 1 u 1 1 1 0 u u u u 0 u
PD 1 u 1 u 0 u u u u u 0 0
Power-on Reset RESET Instruction Brown-out MCLR during Power-Managed Run modes MCLR during Power-Managed Idle modes and Sleep mode WDT Time-out during Full Power or Power-Managed Run modes MCLR during Full Power Execution Stack Full Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Stack Underflow Error (not an actual Reset, STVREN = 0) WDT Time-out during Power-Managed Idle or Sleep modes Interrupt Exit from Power-Managed modes
u(2) u(2) u(2) u(2) u(2) u
(2)
u(2) u(2) u(2)
Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is `1' for POR and unchanged for all other Resets when software BOR is enabled (BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is `0'.
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TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices Power-on Reset, Brown-out Reset ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx ---- 0000 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets ---0 0000 0000 0000 0000 0000 uu-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu ---- 0000 Wake-up via WDT or Interrupt ---0 uuuu(1) uuuu uuuu(1) uuuu uuuu(1) uu-u uuuu(1) ---u uuuu uuuu uuuu PC + 2(3) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(2) uuuu -u-u(2) uu-u u-uu(2) N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---- uuuu
TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR
2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450
4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'.
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TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx 1111 1111 0--- q-00 0-00 0101 ---- ---0 0q-1 11q0 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx xxxx xxxx --00 0000 --00 qqqq 0-00 0000 xxxx xxxx xxxx xxxx --00 0000 0000 0000 0000 0000 0000 0000 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu ---u uuuu 0000 0000 uuuu uuuu 1111 1111 0--- 0-q0 0-00 0101 ---- ---0 0q-q qquu uuuu uuuu uuuu uuuu u0uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu uuuu uuuu --00 0000 --00 qqqq 0-00 0000 uuuu uuuu uuuu uuuu --00 0000 0000 0000 0000 0000 0000 0000 Wake-up via WDT or Interrupt N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- u-qu u-uu uuuu ---- ---u uq-u qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu u-uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON HLVDCON WDTCON RCON(4) TMR1H TMR1L T1CON TMR2 PR2 T2CON ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON SPBRG RCREG TXREG
2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450
4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'.
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TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset 0000 0010 0000 000x 0000 0000 -x-0 x001-1- -1-0-0- -0-0-0- -0--111 -111 -000 -000 -000 -000 ---- -111 1111 1111 11-- -111 1111 1111 -111 1111(5) ---- -xxx xxxx xxxx xx-- -xxx xxxx xxxx -xxx xxxx(5) ---- x000 xxxx xxxx xxxx -xxx xxxx xxxx -x0x 0000(5) ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets 0000 0010 0000 000x 0000 0000 -u-0 u001-1- -1-0-0- -0-0-0- -0--111 -111 -000 -000 -000 -000 ---- -111 1111 1111 11-- -111 1111 1111 -111 1111(5) ---- -uuu uuuu uuuu uu-- -uuu uuuu uuuu -uuu uuuu(5) ---- x000 uuuu uuuu uuuu -uuu uuuu uuuu -u0u 0000(5) ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu 0000 0000 -u-0 u00u-u- -u-u-u- -u--(2) u-u- -u--uuu -uuu -uuu -uuu(2) -uuu -uuu uuuu -uuu uuuu uuuu uu-- -uuu uuuu uuuu -uuu uuuu(5) ---- -uuu uuuu uuuu uu-- -uuu uuuu uuuu -uuu uuuu(5) ---- uuuu uuuu uuuu uuuu -uuu uuuu uuuu -uuu uuuu(5) ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu
TXSTA RCSTA EECON2 EECON1 IPIR2 PIR2 PIE2 IPR1 PIR1 PIE1 TRISE TRISD TRISC TRISB TRISA(5) LATE LATD LATC LATB LATA
(5)
2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450
4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450
PORTE PORTD PORTC PORTB PORTA(5) UEP15 UEP14 UEP13 UEP12 UEP11 UEP10 UEP9
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'.
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TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 00-0 0000 -000 0000 -0x0 000-xxx xxx0--0 0000 0--0 0000 -000 0000 -000 0000 ---- -xxx xxxx xxxx MCLR Resets, WDT Reset, RESET Instruction, Stack Resets ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 00-0 0000 -000 0000 -0x0 000-xxx xxx0--0 0000 0--0 0000 -000 0000 -000 0000 ---- -xxx xxxx xxxx Wake-up via WDT or Interrupt ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu uu-u uuuu -uuu uuuu -uuu uuu-uuu uuuu--u uuuu u--u uuuu -uuu uuuu -uuu uuuu ---- -uuu uuuu uuuu
UEP8 UEP7 UEP6 UEP5 UEP4 UEP3 UEP2 UEP1 UEP0 UCFG UADDR UCON USTAT UEIE UEIR UIE UIR UFRMH UFRML
2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450
4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450 4450
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'.
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5.0 MEMORY ORGANIZATION
5.1 Program Memory Organization
There are two types of memory in PIC18F2450/4450 microcontroller devices: * Program Memory * Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 "Flash Program Memory". PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all `0's (a NOP instruction). The PIC18F2450 and PIC18F4450 each have 16 Kbytes of Flash memory and can store up to 8192 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory maps for PIC18F2450 and PIC18F4450 devices are shown in Figure 5-1.
FIGURE 5-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18F2450/4450 DEVICES
PIC18F2450/4450
PC<20:0> CALL, RCALL, RETURN, RETFIE, RETLW, CALLW, ADDULNK, SUBULNK 21 Stack Level 1
* * *
Stack Level 31 Reset Vector 0000h
High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory 3FFFh 4000h
Read `0'
1FFFFFh 200000h
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5.1.1 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.1.4.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL and GOTO program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-ofStack Special Function Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack. The Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack. The contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `00000'; this is only a Reset value. Status bits indicate if the stack is full, has overflowed or has underflowed.
5.1.2.1
Top-of-Stack Access
5.1.2
RETURN ADDRESS STACK
The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption.
FIGURE 5-2:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack<20:0> 11111 11110 11101
Top-of-Stack Registers TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack 001A34h 000D58h
Stack Pointer STKPTR<4:0> 00010
00011 00010 00001 00000
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5.1.2.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bit. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 18.1 "Configuration Bits" for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and the STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.
5.1.2.3
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value.
REGISTER 5-1:
R/C-0 STKFUL(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STKPTR: STACK POINTER REGISTER
R/C-0 U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
STKUNF(1)
STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as `0' SP4:SP0: Stack Pointer Location bits Bit 7 and bit 6 are cleared by user software or by a POR.
bit 6
bit 5 bit 4-0 Note 1:
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5.1.2.4 Stack Full and Underflow Resets 5.1.4
Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. The STKFUL or STKUNF bits are cleared by user software or a Power-on Reset.
LOOK-UP TABLES IN PROGRAM MEMORY
There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads
5.1.4.1
Computed GOTO
5.1.3
FAST REGISTER STACK
A Fast Register Stack is provided for the STATUS, WREG and BSR registers to provide a "fast return" option for interrupts. Each stack is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. Example 5-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return.
A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value `nn' to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required.
EXAMPLE 5-2:
MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . .
COMPUTED GOTO USING AN OFFSET VALUE
OFFSET, W TABLE PCL nnh nnh nnh
ORG TABLE
5.1.4.2
Table Reads and Table Writes
EXAMPLE 5-1:
CALL SUB1, FAST
FAST REGISTER STACK CODE EXAMPLE
;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK
A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 "Table Reads and Table Writes".
* * SUB1 * * RETURN, FAST
;RESTORE VALUES SAVED ;IN FAST REGISTER STACK
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5.2
5.2.1
PIC18 Instruction Cycle
CLOCKING SCHEME
5.2.2
INSTRUCTION FLOW/PIPELINING
The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-3.
An "Instruction Cycle" consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-3). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 5-3:
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode)
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Internal Phase Clock
PC PC + 2 PC + 4
Execute INST (PC - 2) Fetch INST (PC)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 2) Fetch INST (PC + 4)
EXAMPLE 5-3:
INSTRUCTION PIPELINE FLOW
TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h 2. MOVWF PORTB 3. BRA 4. BSF SUB_1
Fetch 1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Note:
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
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5.2.3 INSTRUCTIONS IN PROGRAM MEMORY
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read `0' (see Section 5.1.1 "Program Counter"). Figure 5-4 shows an example of how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-4 shows how the instruction, GOTO 0006h, is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 19.0 "Instruction Set Summary" provides further details of the instruction set.
FIGURE 5-4:
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1 Program Memory Byte Locations LSB = 0 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h
Instruction 1: Instruction 2: Instruction 3:
MOVLW GOTO MOVFF
055h 0006h 123h, 456h
0Fh EFh F0h C1h F4h
55h 03h 00h 23h 56h
5.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has `1111' as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence, immediately after the first word, the data in the second word is accessed and
used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 5-4 shows how this works. Note: See Section 5.5 "Program Memory and the Extended Instruction Set" for information on two-word instruction in the extended instruction set.
EXAMPLE 5-4:
CASE 1: Object Code
TWO-WORD INSTRUCTIONS
Source Code TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? ; Execute this word as a NOP REG3 ; continue code REG1, REG2 ; No, skip this word
0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 CASE 2: Object Code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000
Source Code TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? ; 2nd word of instruction REG3 ; continue code REG1, REG2 ; Yes, execute this word
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5.3
Note:
Data Memory Organization
The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.6 "Data Memory and the Extended Instruction Set" for more information.
5.3.2
BANK SELECT REGISTER (BSR)
The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. PIC18F2450/ 4450 devices implement three complete banks, for a total of 768 bytes. Figure 5-5 shows the data memory organization for the devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.3 "Access Bank" provides a detailed description of the Access RAM.
Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the 4 Most Significant bits of a location's address; the instruction itself includes the 8 Least Significant bits. Only the four lower bits of the BSR are implemented (BSR3:BSR0). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory. The eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in Figure 5-6. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h, while the BSR is 0Fh, will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 5-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers.
5.3.1
USB RAM
Bank 4 of the data memory is actually mapped to special dual port RAM. When the USB module is disabled, the GPRs in these banks are used like any other GPR in the data memory space. When the USB module is enabled, the memory in this bank is allocated as buffer RAM for USB operation. This area is shared between the microcontroller core and the USB Serial Interface Engine (SIE) and is used to transfer data directly between the two. It is theoretically possible to use this area of USB RAM that is not allocated as USB buffers for normal scratchpad memory or other variable storage. In practice, the dynamic nature of buffer allocation makes this risky at best. Bank 4 is also used for USB buffer management when the module is enabled and should not be used for any other purposes during that time. Additional information on USB RAM and buffer operation is provided in Section 14.0 "Universal Serial Bus (USB)".
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FIGURE 5-5:
BSR<3:0>
DATA MEMORY MAP FOR PIC18F2450/4450 DEVICES
Data Memory Map When a = 0:
= 0000
00h Bank 0 FFh 00h Bank 1 FFh 00h Bank 2 FFh 00h FFh 00h FFh 00h
Access RAM GPR GPR Unused Read as 00h Unused Read as 00h GPR(1)
= 0001
000h 05Fh 060h 0FFh 100h 1FFh 200h 2FFh 300h 3FFh 400h 4FFh 800h
The BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction.
= 0010
= 0011
Bank 3
= 0100
Bank 4
= 0101
Bank 5
Access Bank Access RAM Low
00h
to
5Fh Access RAM High 60h (SFRs) FFh
Unused Read as 00h
= 1110
Bank 14
= 1111
FFh 00h Bank 15 FFh
Unused SFR
EFFh F00h F5Fh F60h FFFh
Note 1:
This bank also serve as RAM buffer for USB operation. See Section 5.3.1 "USB RAM" for more information.
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FIGURE 5-6:
7
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1)
Data Memory
0 000h Bank 0 100h Bank 1 200h Bank 2 300h 00h FFh 00h FFh 00h FFh 00h 7
From Opcode(2)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Bank Select(2)
Bank 3 through Bank 13
E00h Bank 14 F00h Bank 15 FFFh Note 1: 2:
FFh 00h FFh 00h FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction.
5.3.3
ACCESS BANK
While the use of the BSR, with an embedded 8-bit address, allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Block 15. The lower half is known as the "Access RAM" and is composed of GPRs. The upper half is where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 5-5). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0',
however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 5.6.3 "Mapping the Access Bank in Indexed Literal Offset Mode".
5.3.4
GENERAL PURPOSE REGISTER FILE
PIC18 devices may have banked memory in the GPR area. This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets.
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5.3.5 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM in the data memory space. SFRs start at the top of data memory and extend downward to occupy the top segment of Bank 15, from F60h to FFFh. A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and interrupt registers are described in their respective chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's.
TABLE 5-1:
Address FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2450/4450 DEVICES
Name TOSU TOSH TOSL Address FDFh Name INDF2
(1)
Address FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h
Name CCPR1H CCPR1L CCP1CON --
(2)
Address F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h
Name IPR1 PIR1 PIE1 --
(2)
Address F7Fh F7Eh F7Dh F7Ch F7Bh F7Ah F79h F78h F77h F76h F75h F74h F73h F72h F71h F70h F6Fh F6Eh F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h F65h F64h F63h F62h F61h F60h
Name UEP15 UEP14 UEP13 UEP12 UEP11 UEP10 UEP9 UEP8 UEP7 UEP6 UEP5 UEP4 UEP3 UEP2 UEP1 UEP0 UCFG UADDR UCON USTAT UEIE UEIR UIE UIR UFRMH UFRML --(2) --(2) --(2) --(2) --(2) --(2)
FDEh POSTINC2(1) FDDh POSTDEC2(1) FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h PREINC2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON --(2) OSCCON HLVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON --(2) --(2) --(2) --(2) --(2) ADRESH ADRESL ADCON0 ADCON1 ADCON2
(1)
STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0(1)
PLUSW2(1)
--(2) --(2) --(2) BAUDCON --(2) --(2) --(2) --(2) --(2) --(2) --(2) SPBRGH SPBRG RCREG TXREG TXSTA RCSTA --(2) --(2) --(2) EECON2(1) EECON1 --(2) --
(2)
--(2) --(2) --(2) --
(2)
--(2) TRISE(3) TRISD(3) TRISC TRISB TRISA --(2) --
(2)
--(2) --(2) LATE(3) LATD
(3)
FEEh POSTINC0(1) FEDh POSTDEC0(1) FECh FEBh FEAh FE9h FE8h FE7h PREINC0 FSR0H FSR0L WREG INDF1(1)
(1)
PLUSW0(1)
LATC LATB LATA --(2) --(2) --(2) --(2) PORTE PORTD(3) PORTC PORTB PORTA
FE6h POSTINC1(1) FE5h POSTDEC1(1) FE4h FE3h FE2h FE1h FE0h Note 1: 2: 3: PREINC1 FSR1H FSR1L BSR
(1)
PLUSW1(1)
--(2) IPR2 PIR2 PIE2
Not a physical register. Unimplemented registers are read as `0'. These registers are implemented only on 40/44-pin devices.
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TABLE 5-2:
File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON Legend: Note 1: 2: 3: 4: 5: 6:
REGISTER FILE SUMMARY (PIC18F2450/4450)
Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---0 0000 0000 0000 0000 0000 SP4 SP3 SP2 SP1 SP0 00-0 0000 ---0 0000 0000 0000 0000 0000 bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR0IE INTEDG1 -- INT0IE INTEDG2 INT2IE RBIE -- INT1IE TMR0IF TMR0IP -- INT0IF -- INT2IF RBIF RBIP INT1IF 0000 000x 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx Bank Select Register ---- 0000 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx OV Z DC C ---x xxxx 0000 0000 xxxx xxxx T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 Details on page 49, 54 49, 54 49, 54 49, 55 49, 54 49, 54 49, 54 49, 76 49, 76 49, 76 49, 76 49, 83 49, 83 49, 87 49, 88 49, 89 49, 68 49, 69 49, 69 49, 69 49, 69 49, 68 49, 68 49, 49, 68 49, 69 49, 69 49, 69 49, 69 49, 68 49, 68 49, 59 50, 68 50, 69 50, 69 50, 69 50, 69 50, 68 50, 68 50, 66 50, 113 50, 113 50, 111
Top-of-Stack Upper Byte (TOS<20:16>)
Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL -- STKUNF -- -- --
Holding Register for PC<20:16>
Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- --
Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by W -- -- -- -- Indirect Data Memory Address Pointer 0 High Byte
Indirect Data Memory Address Pointer 0 Low Byte Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR1 offset by W -- -- -- -- Indirect Data Memory Address Pointer 1 High Byte
Indirect Data Memory Address Pointer 1 Low Byte -- -- -- --
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by W -- -- -- -- Indirect Data Memory Address Pointer 2 High Byte
Indirect Data Memory Address Pointer 2 Low Byte -- -- -- N
Timer0 Register High Byte Timer0 Register Low Byte TMR0ON T08BIT
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Bit 21 of the TBLPTRU allows access to the device Configuration bits. The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as `0'. These registers and/or bits are not implemented on 28-pin devices and are read as `0'. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as `-'. RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read `0'. RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as `0'. RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
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TABLE 5-2:
File Name OSCCON HLVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON BAUDCON SPBRGH SPBRG RCREG TXREG TXSTA RCSTA EECON2 EECON1 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 TRISE(3) TRISD(3) TRISC TRISB TRISA LATE(3) LATD(3) LATC LATB LATA PORTE PORTD(3) Legend: Note 1: 2: 3: 4: 5: 6:
REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
Bit 7 IDLEN Bit 6 -- -- -- SBOREN(2) Bit 5 -- IRVST -- -- Bit 4 -- HLVDEN -- RI Bit 3 OSTS HLVDL3 -- TO Bit 2 -- HLVDL2 -- PD Bit 1 SCS1 HLVDL1 -- POR Bit 0 SCS0 HLVDL0 SWDTEN BOR Value on POR, BOR 0--- q-00 0-00 0101 --- ---0 0q-1 11q0 xxxx xxxx xxxx xxxx T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000 1111 1111 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx xxxx xxxx CHS3 VCFG1 ACQT2 CHS2 VCFG0 ACQT1 CHS1 PCFG3 ACQT0 CHS0 PCFG2 ADCS2 GO/DONE PCFG1 ADCS1 ADON PCFG0 ADCS0 --00 0000 --00 qqqq 0-00 0000 xxxx xxxx xxxx xxxx DC1B0 SCKP CCP1M3 BRG16 CCP1M2 -- CCP1M1 WUE CCP1M0 ABDEN --00 0000 01-0 0-00 0000 0000 0000 0000 0000 0000 0000 0000 TXEN SREN SYNC CREN SENDB ADDEN BRGH FERR TRMT OERR TX9D RX9D 0000 0010 0000 000x 0000 0000 WRERR -- -- -- -- -- -- -- TRISD3 -- TRISB3 TRISA3 -- LATD3 -- LATB3 LATA3 RE3(5) RD3 WREN HLVDIP HLVDIF HLVDIE CCP1IP CCP1IF CCP1IE TRISE2 TRISD2 TRISC2 TRISB2 TRISA2 LATE2 LATD2 LATC2 LATB2 LATA2 RE2(3) RD2 WR -- -- -- TMR2IP TMR2IF TMR2IE TRISE1 TRISD1 TRISC1 TRISB1 TRISA1 LATE1 LATD1 LATC1 LATB1 LATA1 RE1(3) RD1 -- -- -- -- TMR1IP TMR1IF TMR1IE TRISE0 TRISD0 TRISC0 TRISB0 TRISA0 LATE0 LATD0 LATC0 LATB0 LATA0 RE0(3) RD0 -x-0 x001-1- -1-0-0- -0-0-0- -0--111 -111 -000 -000 -000 -000 ---- -111 1111 1111 11-- -111 1111 1111 -111 1111 ---- -xxx xxxx xxxx xx-- -xxx xxxx xxxx -xxx xxxx ---- x000 xxxx xxxx Details on page 50, 31 50, 183 50, 202 50, 42 50, 119 50, 119 50, 115 50, 122 50, 122 50, 121 50, 182 50, 182 50, 173 50, 174 50, 175 50, 124 50, 124 50, 123, 51, 156, 50, 157 50, 157 50, 164 50, 162 51, 154 51, 155 51, 74 51, 75 51, 95 51, 91 51, 93 51, 94 51, 90 51, 92 51, 110 51, 108 51, 106 51, 103 51, 100 51, 110 51, 108 51, 106 51, 103 51, 100 51, 109 51, 108
VDIRMAG -- IPEN
Timer1 Register High Byte Timer1 Register Low Byte RD16 Timer2 Register Timer2 Period Register -- T2OUTPS3 T1RUN
A/D Result Register High Byte A/D Result Register Low Byte -- -- ADFM -- -- --
Capture/Compare/PWM Register 1 High Byte Capture/Compare/PWM Register 1 Low Byte -- ABDOVF -- RCIDL DC1B1 --
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte EUSART Receive Register EUSART Transmit Register CSRC SPEN TX9 RX9
Data Memory Control Register 2 (not a physical register) -- OSCFIP OSCFIF OSCFIE -- -- -- -- TRISD7 TRISC7 TRISB7 -- -- LATD7 LATC7 LATB7 -- -- RD7 CFGS -- -- -- ADIP ADIF ADIE -- TRISD6 TRISC6 TRISB6 TRISA6(4) -- LATD6 LATC6 LATB6 LATA6(4) -- RD6 -- USBIP USBIF USBIE RCIP RCIF RCIE -- TRISD5 -- TRISB5 TRISA5 -- LATD5 -- LATB5 LATA5 -- RD5 FREE -- -- -- TXIP TXIF TXIE -- TRISD4 -- TRISB4 TRISA4 -- LATD4 -- LATB4 LATA4 -- RD4
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Bit 21 of the TBLPTRU allows access to the device Configuration bits. The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as `0'. These registers and/or bits are not implemented on 28-pin devices and are read as `0'. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as `-'. RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read `0'. RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as `0'. RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
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TABLE 5-2:
File Name PORTC PORTB PORTA UEP15 UEP14 UEP13 UEP12 UEP11 UEP10 UEP9 UEP8 UEP7 UEP6 UEP5 UEP4 UEP3 UEP2 UEP1 UEP0 UCFG UADDR UCON USTAT UEIE UEIR UIE UIR UFRMH UFRML Legend: Note 1: 2: 3: 4: 5: 6:
REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
Bit 7 RC7 RB7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UTEYE -- -- -- BTSEE BTSEF -- -- -- FRM7 Bit 6 RC6 RB6 RA6(4) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UOEMON ADDR6 PPBRST ENDP3 -- -- SOFIE SOFIF -- FRM6 Bit 5 RC5(6) RB5 RA5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADDR5 SE0 ENDP2 -- -- STALLIE STALLIF -- FRM5 Bit 4 RC4(6) RB4 RA4 EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK UPUEN ADDR4 PKTDIS ENDP1 BTOEE BTOEF IDLEIE IDLEIF -- FRM4 Bit 3 -- RB3 RA3 EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS UTRDIS ADDR3 USBEN ENDP0 DFN8EE DFN8EF TRNIE TRNIF -- FRM3 Bit 2 RC2 RB2 RA2 EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN EPOUTEN FSEN ADDR2 RESUME DIR CRC16EE CRC16EF ACTVIE ACTVIF FRM10 FRM2 Bit 1 RC1 RB1 RA1 EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN PPB1 ADDR1 SUSPND PPBI CRC5EE CRC5EF UERRIE UERRIF FRM9 FRM1 Bit 0 RC0 RB0 RA0 EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL PPB0 ADDR0 -- -- PIDEE PIDEF URSTIE URSTIF FRM8 FRM0 Value on POR, BOR xxxx -xxx xxxx xxxx -x0x 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 00-0 0000 -000 0000 -0x0 000-xxx xxx0--0 0000 0--0 0000 -000 0000 -000 0000 ---- -xxx xxxx xxxx Details on page 51, 106 51, 100 51, 100 51, 135 51, 135 51, 135 51, 135 51, 135 51, 135 51, 135 52, 135 52, 135 52, 135 52, 135 52, 135 52, 135 52, 135 52, 135 52, 135 52, 132 52, 136 52, 130 52, 134 52, 147 52, 146 52, 145 52, 144 52, 136 52, 136
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Bit 21 of the TBLPTRU allows access to the device Configuration bits. The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as `0'. These registers and/or bits are not implemented on 28-pin devices and are read as `0'. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as `-'. RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read `0'. RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as `0'. RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
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5.3.6 STATUS REGISTER
The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (`000u u1uu'). It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 19-2 and Table 19-3. Note: The C and DC bits operate as the Borrow and Digit Borrow bits, respectively, in subtraction.
REGISTER 5-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
STATUS REGISTER
U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC(1) R/W-x C(2) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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5.4
Note:
Data Addressing Modes
The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 "Data Memory and the Extended Instruction Set" for more information.
Purpose Register File") or a location in the Access Bank (Section 5.3.3 "Access Bank") as the data source for the instruction. The Access RAM bit `a' determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 5.3.2 "Bank Select Register (BSR)") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register.
While the program memory can be addressed in only one way - through the program counter - information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * * * * Inherent Literal Direct Indirect
An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 5.6.1 "Indexed Addressing with Literal Offset".
5.4.3
INDIRECT ADDRESSING
5.4.1
INHERENT AND LITERAL ADDRESSING
Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address.
Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 5-5.
EXAMPLE 5-5:
5.4.2
DIRECT ADDRESSING
NEXT
HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING
FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer FSR0H, 1 ; All done with ; Bank1? NEXT ; NO, clear next ; YES, continue
Direct Addressing mode specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.4 "General
LFSR CLRF
BTFSS BRA CONTINUE
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5.4.3.1 FSR Registers and the INDF Operand
At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers: FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as "virtual" registers; they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address.
FIGURE 5-7:
INDIRECT ADDRESSING
000h
Using an instruction with one of the indirect addressing registers as the operand....
ADDWF, INDF1, 1 100h
Bank 0 Bank 1 200h Bank 2
...uses the 12-bit address stored in the FSR pair associated with that register....
FSR1H:FSR1L 7 0 7 0
300h
xxxx1110
11001100
Bank 3 through Bank 13
...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. E00h Bank 14 F00h Bank 15 FFFh
Data Memory
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5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW 5.4.3.3 Operations by FSRs on FSRs
In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on it stored value. They are: * POSTDEC: accesses the FSR value, then automatically decrements it by `1' afterwards * POSTINC: accesses the FSR value, then automatically increments it by `1' afterwards * PREINC: increments the FSR value by `1', then uses it in the operation * PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation. In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of INDF1, using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device.
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5.5 Program Memory and the Extended Instruction Set
When using the extended instruction set, this addressing mode requires the following: * The use of the Access Bank is forced (`a' = 0); and * The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation.
The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds eight additional two-word commands to the existing PIC18 instruction set: ADDFSR, ADDULNK, CALLW, MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These instructions are executed as described in Section 5.2.4 "Two-Word Instructions".
5.6
Data Memory and the Extended Instruction Set
Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged.
5.6.2
INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byteoriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they use the Access Bank (Access RAM bit is `1') or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled in shown in Figure 5-8. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 19.2.1 "Extended Instruction Syntax".
5.6.1
INDEXED ADDRESSING WITH LITERAL OFFSET
Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair and its associated file operands. Under the proper conditions, instructions that use the Access Bank - that is, most bit-oriented and byte-oriented instructions - can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode.
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FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as the SFRs or locations F60h to 0FFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode.
000h 060h 080h 100h 00h Bank 1 through Bank 14 60h Valid range for `f' FFh Access RAM Bank 15 F60h SFRs FFFh Data Memory
Bank 0
F00h
When a = 0 and f 5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where `k' is the same as `f'.
000h Bank 0 080h 100h Bank 1 through Bank 14 FSR2H F00h Bank 15 F60h SFRs FFFh Data Memory FSR2L 001001da ffffffff
When a = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space.
000h Bank 0 080h 100h Bank 1 through Bank 14
BSR 00000000
001001da ffffffff
F00h Bank 15 F60h SFRs FFFh Data Memory
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5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode effectively changes how the lower portion of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 5.3.3 "Access Bank"). An example of Access Bank remapping in this addressing mode is shown in Figure 5-9. Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is `1') will continue to use Direct Addressing as before. Any indirect or indexed operation that explicitly uses any of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any instruction that uses the Access Bank, but includes a register address of greater than 05Fh, will use Direct Addressing and the normal Access Bank map.
5.6.4
BSR IN INDEXED LITERAL OFFSET MODE
Although the Access Bank is remapped when the extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described.
FIGURE 5-9:
Example Situation:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING
000h Bank 0 100h 120h 17Fh 200h
ADDWF f, d, a
FSR2H:FSR2L = 120h Locations in the region from the FSR2 Pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). Special Function Registers at F60h through FFFh are mapped to 60h through FFh as usual. Bank 0 addresses below 5Fh are not available in this mode. They can still be addressed by using the BSR.
Window Bank 1 Bank 1 "Window"
00h 5Fh 60h
Bank 2 through Bank 14
SFRs
FFh
Access Bank
F00h Bank 15 F60h SFRs FFFh
Data Memory
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6.0 FLASH PROGRAM MEMORY
6.1 Table Reads and Table Writes
The Flash program memory is readable, writable and erasable, during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 16 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A Bulk Erase operation may not be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT) The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 "Writing to Flash Program Memory". Figure 6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL
Program Memory Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1:
Table Pointer register points to a byte in program memory.
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FIGURE 6-2: TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1:
Table Pointer actually points to one of 16 holding registers, the address of which is determined by TBLPTRL<3:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 "Writing to Flash Program Memory".
6.2
Control Registers
Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers
The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WREN bit is set and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset or a write operation was attempted improperly.
6.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 6-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory.
The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation.
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REGISTER 6-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EECON1: MEMORY CONTROL REGISTER 1
R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR(1) R/W-0 WREN R/S-0 WR U-0 -- bit 0
Unimplemented: Read as `0' CFGS: Flash Program or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only WRERR: Flash Program Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program 0 = Inhibits write cycles to Flash program WR: Write Control bit 1 = Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle complete Unimplemented: Read as `0' When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition.
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0 Note 1:
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6.2.2 TABLE LATCH REGISTER (TABLAT) 6.2.4 TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. When a TBLWT is executed, the four LSbs of the Table Pointer register (TBLPTR<3:0>) determine which of the 16 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 16 MSbs of the TBLPTR (TBLPTR<21:4>) determine which program memory block of 16 bytes is written to. For more detail, see Section 6.5 "Writing to Flash Program Memory". When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 6-3 describes the relevant boundaries of the TBLPTR based on Flash program memory operations.
6.2.3
TABLE POINTER REGISTER (TBLPTR)
The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the Configuration bits. The Table Pointer, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low-order 21 bits.
TABLE 6-1:
Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+*
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write
FIGURE 6-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0
TABLE ERASE TBLPTR<21:6> TABLE WRITE - TBLPTR<21:4> TABLE READ - TBLPTR<21:0>
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6.3 Reading the Flash Program Memory
TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT.
The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register (IR)
FETCH
TBLRD
TABLAT Read Register
EXAMPLE 6-1:
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD
READING A FLASH PROGRAM MEMORY WORD
CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word
TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVF
TABLAT, W WORD_EVEN TABLAT, W WORD_ODD
; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data
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6.4 Erasing Flash Program Memory
6.4.1
The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. The EECON1 register commands the erase operation. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.
FLASH PROGRAM MEMORY ERASE SEQUENCE
The sequence of events for erasing a block of internal program memory is: 1. 2. Load Table Pointer register with address of row being erased. Set the EECON1 register for the erase operation: * clear the CFGS bit to access program memory; * set WREN bit to enable writes; * set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the Row Erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Re-enable interrupts.
3. 4. 5. 6. 7. 8.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, CFGS WREN FREE GIE ; load TBLPTR with the base ; address of the memory block
ERASE_ROW BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF ; ; ; ; access Flash program memory enable write to memory enable Row Erase operation disable interrupts
Required Sequence
; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts
WR GIE
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6.5 Writing to Flash Program Memory
The minimum programming block is 8 words or 16 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 16 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 16 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 16 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note: The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a `0' to a `1'. When modifying individual bytes, it is not necessary to load all 16 holding registers before executing a write operation.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT Write Register
8
TBLPTR = xxxxx0 TBLPTR = xxxxx1
8
TBLPTR = xxxxx2
8
TBLPTR = xxxxxF
8
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
6.5.1
FLASH PROGRAM MEMORY WRITE SEQUENCE
The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer register with address being erased. Execute the Row Erase procedure. Load Table Pointer register with address of first byte being written. Write 16 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * clear the CFGS bit to access program memory; * set WREN to enable byte writes. Disable interrupts. Write 55h to EECON2.
10. Write 0AAh to EECON2. 11. Set the WR bit. This will begin the write cycle. 12. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Re-enable interrupts. 14. Repeat steps 6 through 14 once more to write 64 bytes. 15. Verify the memory (table read). This procedure will require about 8 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 16 bytes in the holding register.
8. 9.
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_BLOCK TBLRD*+ MOVF MOVWF DECFSZ BRA MODIFY_WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF TBLRD*MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF WRITE_BUFFER_BACK MOVLW MOVWF WRITE_BYTE_TO_HREGS MOVF MOVWF TBLWT+* Required Sequence CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, CFGS EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L D'4' COUNTER1 D'16' COUNTER POSTINC0, W TABLAT ; load TBLPTR with the base ; address of the memory block DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer TABLAT, W POSTINC0 COUNTER READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat D'64' COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block ; point to buffer
; Load TBLPTR with the base ; address of the memory block
; update buffer word
; ; ; ;
access Flash program memory enable write to memory enable Row Erase operation disable interrupts
; write 55h ; ; ; ; ; write 0AAh start erase (CPU stall) re-enable interrupts dummy read decrement point to buffer
; number of bytes in holding register
DECFSZ COUNTER BRA WRITE_WORD_TO_HREGS
; ; ; ; ;
get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full
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EXAMPLE 6-3:
PROGRAM_MEMORY BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF DECFSZ BRA BSF BCF EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR COUNTER1 WRITE_BUFFER_BACK INTCON, GIE EECON1, WREN ; access Flash program memory ; enable write to memory ; disable interrupts
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
Required Sequence
; write 55h ; write 0AAh ; start program (CPU stall)
; re-enable interrupts ; disable write to memory
6.5.2
WRITE VERIFY
6.5.4
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.
PROTECTION AGAINST SPURIOUS WRITES
To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 18.0 "Special Features of the CPU" for more detail.
6.5.3
UNEXPECTED TERMINATION OF WRITE OPERATION
6.6
Flash Program Operation During Code Protection
If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed.
See Section 18.5 "Program Verification and Code Protection" for details on code protection of Flash program memory.
TABLE 6-2:
Name TBLPTRU
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 7 -- Bit 6 -- Bit 5 bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page 49 49 49 49 INT0IE FREE -- -- -- RBIE WRERR -- -- -- TMR0IF WREN HLVDIP HLVDIF HLVDIE INT0IF WR -- -- -- RBIF -- -- -- -- 49 51 51 51 51 51
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT INTCON EECON2 EECON1 IPR2 PIR2 PIE2 Program Memory Table Latch GIE/GIEH PEIE/GIEL TMR0IE -- OSCFIP OSCFIF OSCFIE CFGS -- -- -- -- USBIP USBIF USBIE Control Register 2 (not a physical register)
Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash access.
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7.0
7.1
8 x 8 HARDWARE MULTIPLIER
Introduction
EXAMPLE 7-1:
MOVF MULWF ARG1, W ARG2
8 x 8 UNSIGNED MULTIPLY ROUTINE
; ; ARG1 * ARG2 -> ; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 7-1.
EXAMPLE 7-2:
MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F
8 x 8 SIGNED MULTIPLY ROUTINE
; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1
; Test Sign Bit ; PRODH = PRODH ; - ARG2
7.2
Operation
Example 7-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 7-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done.
TABLE 7-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 28 52 35 Cycles (Max) 69 1 91 6 242 28 254 40 Time @ 40 MHz 6.9 s 100 ns 9.1 s 600 ns 24.2 s 2.8 s 25.4 s 4.0 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 11.2 s 102.6 s 16.0 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 28 s 254 s 40 s
8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed
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Example 7-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
EQUATION 7-2:
16 x 16 SIGNED MULTIPLICATION ALGORITHM
EQUATION 7-1:
16 x 16 UNSIGNED MULTIPLICATION ALGORITHM
ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L)
RES3:RES0
= =
RES3:RES0= ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216)
EXAMPLE 7-4:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS BRA MOVF SUBWF MOVF SUBWFB ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE :
16 x 16 SIGNED MULTIPLY ROUTINE
; ARG1L * ARG2L -> ; PRODH:PRODL ; ;
EXAMPLE 7-3:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC
16 x 16 UNSIGNED MULTIPLY ROUTINE
; ARG1L * ARG2L-> ; PRODH:PRODL ; ;
ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L,W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3
ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F
; ARG1H * ARG2H-> ; PRODH:PRODL ; ;
; ARG1H * ARG2H -> ; PRODH:PRODL ; ;
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H-> PRODH:PRODL Add cross products
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H -> PRODH:PRODL Add cross products
ARG1H * ARG2L -> PRODH:PRODL Add cross products
ARG1H * ARG2L-> PRODH:PRODL Add cross products
Example 7-4 shows the sequence to do a 16 x 16 signed multiply. Equation 7-2 shows the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done.
; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ;
ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3
; ARG1H:ARG1L neg? ; no, done ; ; ;
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8.0 INTERRUPTS
The PIC18F2450/4450 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2 PIE1, PIE2 IPR1, IPR2 When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used) which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.
It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. Each interrupt source has three bits to control its operation. The functions of these bits are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode.
8.1
USB Interrupts
Unlike other peripherals, the USB module is capable of generating a wide range of interrupts for many types of events. These include several types of normal communication and status events and several module level error events. To handle these events, the USB module is equipped with its own interrupt logic. The logic functions in a manner similar to the microcontroller level interrupt funnel, with each interrupt source having separate flag and enable bits. All events are funneled to a single device level interrupt, USBIF (PIR2<5>). Unlike the device level interrupt logic, the individual USB interrupt events cannot be individually assigned their own priority. This is determined at the device level interrupt funnel for all USB events by the USBIP bit. For additional details on USB interrupt logic, refer to Section 14.5 "USB Interrupts".
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FIGURE 8-1: INTERRUPT LOGIC
TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP
Wake-up if in Sleep Mode
Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP From USB Interrupt Logic USBIF USBIE USBIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation
Interrupt to CPU Vector to Location 0008h
GIE/GIEH IPEN IPEN PEIE/GIEL IPEN
Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP Interrupt to CPU Vector to Location 0018h
TMR1IF TMR1IE TMR1IP From USB Interrupt Logic USBIF USBIE USBIP
PEIE/GIEL GIE/GIEH
Additional Peripheral Interrupts
INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP
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8.2 INTCON Registers
Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
REGISTER 8-1:
R/W-0 GIE/GIEH bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF(1) bit 0
PEIE/GIEL
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 8-2:
R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1 INTEDG0 R/W-1 INTEDG1 R/W-1 INTEDG2 U-0 -- R/W-1 TMR0IP U-0 -- R/W-1 RBIP bit 0
RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge Unimplemented: Read as `0' TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
Note:
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REGISTER 8-3:
R/W-1 INT2IP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1 INT1IP U-0 -- R/W-0 INT2IE R/W-0 INT1IE U-0 -- R/W-0 INT2IF R/W-0 INT1IF bit 0
INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt Unimplemented: Read as `0' INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
Note:
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8.3 PIR Registers
The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt.
REGISTER 8-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0 ADIF R-0 RCIF R-0 TXIF U-0 -- R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full Unimplemented: Read as `0' CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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REGISTER 8-5:
R/W-0 OSCFIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
U-0 -- R/W-0 USBIF U-0 -- U-0 -- R/W-0 HLVDIF U-0 -- U-0 -- bit 0
OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software) 0 = System clock operating Unimplemented: Read as `0' USBIF: USB Interrupt Flag bit 1 = USB has requested an interrupt (must be cleared in software) 0 = No USB interrupt request Unimplemented: Read as `0' HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A high/low-voltage condition occurred 0 = No high/low-voltage event has occurred Unimplemented: Read as `0'
bit 6 bit 5
bit 4-3 bit 2
bit 1-0
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8.4 PIE Registers
The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
REGISTER 8-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE U-0 -- R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt Unimplemented: Read as `0' CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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REGISTER 8-7:
R/W-0 OSCFIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0 -- R/W-0 USBIE U-0 -- U-0 -- R/W-0 HLVDIE U-0 -- U-0 -- bit 0
OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' USBIE: USB Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0'
bit 6 bit 5
bit 4-3 bit 2
bit 1-0
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8.5 IPR Registers
The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
REGISTER 8-8:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1 ADIP R/W-1 RCIP R/W-1 TXIP U-0 -- R/W-1 CCP1IP R/W-1 TMR2IP R/W-1 TMR1IP bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority
bit 5
bit 4
bit 3 bit 2
Unimplemented: Read as `0' CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority
bit 1
bit 0
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REGISTER 8-9:
R/W-1 OSCFIP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0 -- R/W-1 USBIP U-0 -- U-0 -- R/W-1 HLVDIP U-0 -- U-0 -- bit 0
OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' USBIP: USB Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0'
bit 6 bit 5
bit 4-3 bit 2
bit 1-0
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8.6 RCON Register
The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities.
REGISTER 8-10:
R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
RCON: RESET CONTROL REGISTER
U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0(2) POR R/W-0 BOR bit 0
R/W-1(1) SBOREN
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) SBOREN: BOR Software Enable bit(1) For details of bit operation, see Register 4-1. Unimplemented: Read as `0' RI: RESET Instruction Flag bit For details of bit operation, see Register 4-1. TO: Watchdog Time-out Flag bit For details of bit operation, see Register 4-1. PD: Power-Down Detection Flag bit For details of bit operation, see Register 4-1. POR: Power-on Reset Status bit(2) For details of bit operation, see Register 4-1. BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. If SBOREN is enabled, its Reset state is `1'; otherwise, it is `0'. See Register 4-1 for additional information. The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional information.
bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Note 1: 2:
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8.7 INTn Pin Interrupts 8.8 TMR0 Interrupt
External interrupts on the RB0/AN12/INT0, RB1/AN10/ INT1and RB2/AN8/INT2/VMO pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE. Flag bit, INTxIF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wakeup the processor from the power-managed modes if bit, INTxIE, was set prior to going into the power-managed modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high priority interrupt source. In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 12.0 "Timer2 Module" for further details on the Timer0 module.
8.9
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>).
8.10
Context Saving During Interrupts
During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 5.3 "Data Memory Organization"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine.
EXAMPLE 8-1:
MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere
W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS
; Restore BSR ; Restore WREG ; Restore STATUS
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NOTES:
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9.0 I/O PORTS
Reading the PORTA register reads the status of the pins; writing to it will write to the port latch. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA6 pin is multiplexed with the main oscillator pin; it is enabled as an oscillator or I/O pin by the selection of the main oscillator in Configuration Register 1H (see Section 18.1 "Configuration Bits" for details). When not used as a port pin, RA6 and its associated TRIS and LAT bits are read as `0'. RA4 is also multiplexed with the USB module; it serves as a receiver input from an external USB transceiver. For details on configuration of the USB module, see Section 14.2 "USB Status and Control". Several PORTA pins are multiplexed with analog inputs. The operation of pins RA5 and RA3:RA0 as A/D converter inputs is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). Note: On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read as `0'. RA4 is configured as a digital input. Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (data direction register) * PORT register (reads the levels on the pins of the device) * LAT register (output latch) The Data Latch register (LATA) is useful for readmodify-write operations on the value driven by the I/O pins. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 9-1.
FIGURE 9-1:
GENERIC I/O PORT OPERATION
RD LAT Data Bus WR LAT or PORT
D
Q I/O pin(1)
CK Data Latch D Q
All other PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
WR TRIS
CK TRIS Latch Input Buffer
EXAMPLE 9-1:
CLRF ; ; ; LATA ; ; ; 0Fh ; ADCON1 ; 0CFh ; ; ; TRISA ; ; PORTA
INITIALIZING PORTA
Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs
RD TRIS
CLRF
Q D EN EN RD PORT Note 1: I/O pins have diode protection to VDD and VSS.
MOVLW MOVWF MOVLW
MOVWF
9.1
PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin).
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TABLE 9-1:
Pin RA0/AN0
PORTA I/O SUMMARY
Function RA0 AN0 TRIS Setting 0 1 1 0 1 AN1 1 0 1 AN2 VREF1 1 0 1 AN3 VREF+ 1 1 0 1 T0CKI RCV 1 x 0 1 AN4 HLVDIN OSC2 CLKO RA6 1 1 x x 0 1 I/O OUT IN IN OUT IN IN OUT IN IN IN OUT IN IN IN OUT IN IN IN OUT IN IN IN OUT OUT OUT IN I/O Type DIG TTL ANA DIG TTL ANA DIG TTL ANA ANA DIG TTL ANA ANA DIG ST ST TTL DIG TTL ANA ANA ANA DIG DIG TTL Description LATA<0> data output; not affected by analog input. PORTA<0> data input; disabled when analog input enabled. A/D input channel 0. Default configuration on POR; does not affect digital output. LATA<1> data output; not affected by analog input. PORTA<1> data input; reads `0' on POR. A/D input channel 1. Default configuration on POR; does not affect digital output. LATA<2> data output; not affected by analog input. PORTA<2> data input. Disabled when analog functions enabled. A/D input channel 2. Default configuration on POR; not affected by analog output. A/D voltage reference low input. LATA<3> data output; not affected by analog input. PORTA<3> data input; disabled when analog input enabled. A/D input channel 3. Default configuration on POR. A/D voltage reference high input. LATA<4> data output; not affected by analog input. PORTA<4> data input; disabled when analog input enabled. Timer0 clock input. External USB transceiver RCV input. LATA<5> data output; not affected by analog input. PORTA<5> data input; disabled when analog input enabled. A/D input channel 4. Default configuration on POR. High/Low-Voltage Detect external trip point input. Main oscillator feedback output connection (all XT and HS modes). System cycle clock output (FOSC/4); available in EC, ECPLL and INTCKO modes. LATA<6> data output. Available only in ECIO, ECPIO and INTIO modes; otherwise, reads as `0'. PORTA<6> data input. Available only in ECIO, ECPIO and INTIO modes; otherwise, reads as `0'.
RA1/AN1
RA1
RA2/AN2/ VREF-
RA2
RA3/AN3/ VREF+
RA3
RA4/T0CKI/ RCV
RA4
RA5/AN4/ HLVDIN
RA5
OSC2/CLKO/ RA6
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option)
TABLE 9-2:
Name PORTA LATA TRISA ADCON1 UCON
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- -- -- -- Bit 6 RA6(1) LATA6 -- PPBRST
(1)
Bit 5 RA5 LATA5 TRISA5 VCFG1 SE0
Bit 4 RA4 LATA4 TRISA4 VCFG0 PKTDIS
Bit 3 RA3 LATA3 TRISA3 PCFG3 USBEN
Bit 2 RA2 LATA2 TRISA2 PCFG2
Bit 1 RA1 LATA1 TRISA1 PCFG1
Bit 0 RA0 LATA0 TRISA0 PCFG0 --
Reset Values on page 51 51 51 50 52
TRISA6(1)
RESUME SUSPND
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTA. Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'.
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9.2 PORTB, TRISB and LATB Registers
A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. Pins, RB2 and RB3, are multiplexed with the USB peripheral and serve as the differential signal outputs for an external USB transceiver (TRIS configuration). Refer to Section 14.2.2.2 "External Transceiver" for additional information on configuring the USB module for operation with an external transceiver.
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, RB4:RB0 are configured as analog inputs by default and read as `0'; RB7:RB5 are configured as digital inputs. By programming the Configuration bit, PBADEN (CONFIG3H<1>), RB4:RB0 will alternatively be configured as digital inputs on POR. Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur. Any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison. The pins are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). The interrupt-on-change can be used to wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). This will end the mismatch condition. Clear flag bit, RBIF.
EXAMPLE 9-2:
CLRF PORTB ; ; ; LATB ; ; ; 0Eh ; ADCON1 ; ; ; 0CFh ; ; ; TRISB ; ; ;
INITIALIZING PORTB
Initialize PORTB by clearing output data latches Alternate method to clear output data latches Set RB<4:0> as digital I/O pins (required if config bit PBADEN is set) Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
CLRF
MOVLW MOVWF
MOVLW
MOVWF
b)
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TABLE 9-3:
Pin RB0/AN12/ INT0
PORTB I/O SUMMARY
Function RB0 TRIS Setting 0 1 AN12 INT0 1 1 0 1 AN10 INT1 1 1 0 1 AN8 INT2 VMO 1 1 0 0 1 AN9 VPO 1 0 0 1 AN11 KBI0 1 1 0 1 KBI1 PGM 1 x 0 1 KBI2 PGC 1 x 0 1 KBI3 PGD 1 x x I/O OUT IN IN IN OUT IN IN IN OUT IN IN IN OUT OUT IN IN OUT OUT IN IN IN OUT IN IN IN OUT IN IN IN OUT IN IN OUT IN I/O Type DIG TTL ANA ST DIG TTL ANA ST DIG TTL ANA ST DIG DIG TTL ANA DIG DIG TTL ANA TTL DIG TTL TTL ST DIG TTL TTL ST DIG TTL TTL DIG ST Description LATB<0> data output; not affected by analog input. PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) A/D input channel 12.(1) External interrupt 0 input. LATB<1> data output; not affected by analog input. PORTB<1> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) A/D input channel 10.(1) External interrupt 1 input. LATB<2> data output; not affected by analog input. PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) A/D input channel 8.(1) External interrupt 2 input. External USB transceiver VMO data output. LATB<3> data output; not affected by analog input. PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) A/D input channel 9.(1) External USB transceiver VPO data output. LATB<4> data output; not affected by analog input. PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) A/D input channel 11.(1) Interrupt-on-pin change. LATB<5> data output. PORTB<5> data input; weak pull-up when RBPU bit is cleared. Interrupt-on-pin change. Single-Supply Programming mode entry (ICSPTM). Enabled by LVP Configuration bit; all other pin functions disabled. LATB<6> data output. PORTB<6> data input; weak pull-up when RBPU bit is cleared. Interrupt-on-pin change. Serial execution (ICSP) clock input for ICSP and ICD operation.(2) LATB<7> data output. PORTB<7> data input; weak pull-up when RBPU bit is cleared. Interrupt-on-pin change. Serial execution data output for ICSP and ICD operation.(2) Serial execution data input for ICSP and ICD operation.(2)
RB1/AN10/ INT1
RB1
RB2/AN8/ INT2/VMO
RB2
RB3/AN9/VPO
RB3
RB4/AN11/ KBI0
RB4
RB5/KBI1/ PGM
RB5
RB6/KBI2/ PGC
RB6
RB7/KBI3/ PGD
RB7
Legend: Note 1: 2:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when PBADEN is set and digital inputs when PBADEN is cleared. All other pin functions are disabled when ICSPTM or ICD operation is enabled.
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TABLE 9-4:
Name PORTB LATB TRISB INTCON INTCON2 INTCON3 ADCON1 UCON
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 LATB7 TRISB7 RBPU INT2IP -- -- Bit 6 RB6 LATB6 TRISB6 Bit 5 RB5 LATB5 TRISB5 TMR0IE -- VCFG1 SE0 Bit 4 RB4 LATB4 TRISB4 INT0IE INT2IE VCFG0 PKTDIS Bit 3 RB3 LATB3 TRISB3 RBIE -- INT1IE PCFG3 USBEN Bit 2 RB2 LATB2 TRISB2 TMR0IF TMR0IP -- PCFG2 Bit 1 RB1 LATB1 TRISB1 INT0IF -- INT2IF PCFG1 Bit 0 RB0 LATB0 TRISB0 RBIF RBIP INT1IF PCFG0 -- Reset Values on page 51 51 51 49 49 49 50 52
GIE/GIEH PEIE/GIEL INT1IP -- PPBRST
INTEDG0 INTEDG1 INTEDG2
RESUME SUSPND
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTB.
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9.3 PORTC, TRISC and LATC Registers
When enabling peripheral functions on PORTC pins other than RC4 and RC5, care should be taken in defining the TRIS bits. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins, except RC4 and RC5, are configured as digital inputs. To use pins RC4 and RC5 as digital inputs, the USB module must be disabled (UCON<3> = 0) and the on-chip USB transceiver must be disabled (UCFG<3> = 1).
PORTC is a 7-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). In PIC18F2450/4450 devices, the RC3 pin is not implemented. The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is primarily multiplexed with serial communication modules, including the EUSART and the USB module (Table 9-5). Except for RC4 and RC5, PORTC uses Schmitt Trigger input buffers. Pins RC4 and RC5 are multiplexed with the USB module. Depending on the configuration of the module, they can serve as the differential data lines for the onchip USB transceiver, or the data inputs from an external USB transceiver. Both RC4 and RC5 have TTL input buffers instead of the Schmitt Trigger buffers on the other pins. Unlike other PORTC pins, RC4 and RC5 do not have TRISC bits associated with them. As digital ports, they can only function as digital inputs. When configured for USB operation, the data direction is determined by the configuration and status of the USB module at a given time. If an external transceiver is used, RC4 and RC5 always function as inputs from the transceiver. If the on-chip transceiver is used, the data direction is determined by the operation being performed by the module at that time. When the external transceiver is enabled, RC2 also serves as the output enable control to the transceiver. Additional information on configuring USB options is provided in Section 14.2.2.2 "External Transceiver".
The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins.
EXAMPLE 9-3:
CLRF PORTC ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTC
Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction RC<5:0> as outputs RC<7:6> as inputs
CLRF
LATC
MOVLW
07h
MOVWF
TRISC
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TABLE 9-5:
Pin RC0/T1OSO/ T1CKI
PORTC I/O SUMMARY
Function RC0 T1OSO T1CKI TRIS Setting 0 1 x 1 0 1 T1OSI UOE x 0 0 1 CCP1 0 1 --(1) --(1) --(1) VM --
(1)
I/O OUT IN OUT IN OUT IN IN OUT OUT IN OUT IN IN OUT IN IN IN OUT IN IN OUT IN OUT OUT IN OUT IN IN OUT IN
I/O Type DIG ST ANA ST DIG ST ANA DIG DIG ST DIG ST TTL XCVR XCVR TTL TTL XCVR XCVR TTL DIG ST DIG DIG ST DIG ST ST DIG ST LATC<0> data output. PORTC<0> data input.
Description
Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. Timer1 counter input. LATC<1> data output. PORTC<1> data input. Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. External USB transceiver OE output. LATC<2> data output. PORTC<2> data input. CCP1 Compare and PWM output; takes priority over port data. CCP1 Capture input. PORTC<4> data input; disabled when USB module or on-chip transceiver is enabled. USB bus differential minus line output (internal transceiver). USB bus differential minus line input (internal transceiver). External USB transceiver VM input. PORTC<5> data input; disabled when USB module or on-chip transceiver is enabled. USB bus differential plus line output (internal transceiver). USB bus differential plus line input (internal transceiver). External USB transceiver VP input. LATC<6> data output. PORTC<6> data input. Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. Synchronous serial clock output (EUSART module); takes priority over port data. Synchronous serial clock input (EUSART module). LATC<7> data output. PORTC<7> data input. Asynchronous serial receive data input (EUSART module). Synchronous serial data output (EUSART module). Synchronous serial data input (EUSART module). User must configure as an input.
RC1/T1OSI/ UOE
RC1
RC2/CCP1
RC2
RC4/D-/VM
RC4 D-
RC5/D+/VP
RC5 D+ VP
--(1) --(1) --1) --1) 0 1
RC6/TX/CK
RC6 TX CK
0 0 1
RC7/RX/DT
RC7 RX DT
0 1 1 1 1
Legend:
Note 1:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, XCVR = USB Transceiver, x = Don't care (TRIS bit does not affect port direction or is overridden for this option) RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is determined by the USB configuration.
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TABLE 9-6:
Name PORTC LATC TRISC UCON
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 LATC7 TRISC7 -- Bit 6 RC6 LATC6 TRISC6 PPBRST Bit 5 RC5(1) -- -- SE0 Bit 4 RC4(1) -- -- PKTDIS Bit 3 -- -- -- USBEN Bit 2 RC2 LATC2 TRISC2 Bit 1 RC1 LATC1 TRISC1 Bit 0 RC0 LATC0 TRISC0 -- Reset Values on page 51 51 51 52
RESUME SUSPND
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTC. Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
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9.4
Note:
PORTD, TRISD and LATD Registers
PORTD is only available on 40/44-pin devices.
EXAMPLE 9-4:
CLRF PORTD ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTD
Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs
CLRF
LATD
PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs.
MOVLW
0CFh
MOVWF
TRISD
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TABLE 9-7:
Pin
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 Legend:
PORTD I/O SUMMARY
Function
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
TRIS Setting
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
I/O
OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN
I/O Type
DIG ST DIG ST DIG ST DIG ST DIG ST DIG ST DIG ST DIG ST LATD<0> data output. PORTD<0> data input. LATD<1> data output. PORTD<1> data input. LATD<2> data output. PORTD<2> data input. LATD<3> data output. PORTD<3> data input. LATD<4> data output. PORTD<4> data input. LATD<5> data output PORTD<5> data input LATD<6> data output. PORTD<6> data input. LATD<7> data output. PORTD<7> data input.
Description
OUT = Output, IN = Input, DIG = Digital Output, ST = Schmitt Buffer Input
TABLE 9-8:
Name PORTD(1) LATD(1) TRISD(1) Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7 RD7 LATD7 TRISD7 Bit 6 RD6 LATD6 TRISD6 Bit 5 RD5 LATD5 TRISD5 Bit 4 RD4 LATD4 TRISD4 Bit 3 RD3 LATD3 TRISD3 Bit 2 RD2 LATD2 TRISD2 Bit 1 RD1 LATD1 TRISD1 Bit 0 RD0 LATD0 TRISD0 Reset Values on page 51 51 51
These registers and/or bits are unimplemented on 28-pin devices.
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9.5 PORTE, TRISE and LATE Registers
functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device's Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. Note: On a Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled.
Depending on the particular PIC18F2450/4450 device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/AN5, RE1/AN6 and RE2/AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as `0's. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, RE2:RE0 are configured as analog inputs.
EXAMPLE 9-5:
CLRF PORTE ; ; ; LATE ; ; ; 0Ah ; ADCON1 ; 03h ; ; ; TRISC ; ; ;
INITIALIZING PORTE
Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RE<0> as inputs RE<1> as inputs RE<2> as outputs
CLRF
MOVLW MOVWF MOVLW
MOVWF
The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. The fourth pin of PORTE (MCLR/VPP/RE3) is an input only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it
9.5.1
PORTE IN 28-PIN DEVICES
For 28-pin devices, PORTE is only available when Master Clear functionality is disabled (MCLRE = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described.
REGISTER 9-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3-0 Note 1: 2: 3:
PORTE REGISTER
U-0 -- U-0 -- U-0 -- R/W-x RE3(1,2) R/W-0 RE2(3) R/W-0 RE1(3) R/W-0 RE0(3) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RE3:RE0: PORTE Data Input bits(1,2,3) implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise, read as `0'. RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). Unimplemented in 28-pin devices; read as `0'.
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TABLE 9-9:
Pin RE0/AN5
PORTE I/O SUMMARY
Function RE0 AN5 TRIS Setting 0 1 1 0 1 AN6 1 0 1 AN7 1 -- (1) --(1) -- (1) I/O OUT IN IN OUT IN IN OUT IN IN IN IN IN I/O Type DIG ST ANA DIG ST ANA DIG ST ANA ST ST ANA Description LATE<0> data output; not affected by analog input. PORTE<0> data input; disabled when analog input enabled. A/D input channel 5; default configuration on POR. LATE<1> data output; not affected by analog input. PORTE<1> data input; disabled when analog input enabled. A/D input channel 6; default configuration on POR. LATE<2> data output; not affected by analog input. PORTE<2> data input; disabled when analog input enabled. A/D input channel 7; default configuration on POR. PORTE<3> data input; enabled when MCLRE Configuration bit is clear. External Master Clear input; enabled when MCLRE Configuration bit is set. High-voltage detection, used for ICSPTM mode entry detection. Always available regardless of pin mode.
RE1/AN6
RE1
RE2/AN7
RE2
MCLR/VPP/ RE3
RE3 MCLR VPP
Legend: Note 1:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input. RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
TABLE 9-10:
Name PORTE LATE(3) TRISE
(3)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7 -- -- -- -- Bit 6 -- -- -- -- Bit 5 -- -- -- VCFG1 Bit 4 -- -- -- VCFG0 Bit 3 RE3(1,2) -- -- PCFG3 Bit 2 RE2(3) LATE2 TRISE2 PCFG2 Bit 1 RE1(3) LATE1 TRISE1 PCFG1 Bit 0 RE0(3) LATE0 TRISE0 PCFG0 Reset Values on page 51 51 51 50
ADCON1
Legend: -- = unimplemented, read as `0' Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise, read as `0'. 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). 3: These registers and/or bits are unimplemented on 28-pin devices.
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10.0 TIMER0 MODULE
The Timer0 module incorporates the following features: * Software selectable operation as a timer or counter in both 8-Bit or 16-Bit modes * Readable and writable registers * Dedicated 8-bit, software programmable prescaler * Selectable clock source (internal or external) * Edge select for external clock * Interrupt on overflow The T0CON register (Register 10-1) controls all aspects of the module's operation, including the prescale selection. It is both readable and writable. A simplified block diagram of the Timer0 module in 8-Bit mode is shown in Figure 10-1. Figure 10-2 shows a simplified block diagram of the Timer0 module in 16Bit mode.
REGISTER 10-1:
R/W-1 TMR0ON bit 7 Legend: R = Readable bit -n = Value at POR bit 7
T0CON: TIMER0 CONTROL REGISTER
R/W-1 T08BIT R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value
bit 6
bit 5
bit 4
bit 3
bit 2-0
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10.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode, the module increments on every clock by default unless a different prescaler value is selected (see Section 10.3 "Prescaler"). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In Counter mode, Timer0 increments either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter.
10.2
Timer0 Reads and Writes in 16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-Bit mode; it is actually a buffered version of the real high byte of Timer0, which is not directly readable nor writable (refer to Figure 10-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once.
FIGURE 10-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4 0 1 1 Sync with Internal Clocks (2 TCY Delay) 8 8 Internal Data Bus TMR0L Set TMR0IF on Overflow
T0CKI pin T0SE T0CS T0PS2:T0PS0 PSA
Programmable Prescaler 3
0
Note:
Upon Reset, Timer0 is enabled in 8-Bit mode with clock input from T0CKI maximum prescale.
FIGURE 10-2:
FOSC/4
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0 1 1 Sync with Internal Clocks (2 TCY Delay) Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus TMR0L TMR0 High Byte 8 Set TMR0IF on Overflow
T0CKI pin T0SE T0CS T0PS2:T0PS0 PSA
Programmable Prescaler 3
0
Note:
Upon Reset, Timer0 is enabled in 8-Bit mode with clock input from T0CKI maximum prescale.
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10.3 Prescaler
10.3.1
An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS2:T0PS0 bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256, in power-of-2 increments, are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0,etc.) clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment.
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control and can be changed "on-the-fly" during program execution.
10.4
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-Bit mode, or from FFFFh to 0000h in 16-Bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before reenabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep.
TABLE 10-1:
Name TMR0L TMR0H INTCON T0CON TRISA
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page 50 50 INT0IE T0SE TRISA4 RBIE PSA TRISA3 TMR0IF T0PS2 TRISA2 INT0IF T0PS1 TRISA1 RBIF T0PS0 TRISA0 49 50 51 T0CS TRISA5
Timer0 Register Low Byte Timer0 Register High Byte GIE/GIEH PEIE/GIEL TMR0IE TMR0ON -- T08BIT TRISA6(1)
Legend: -- = unimplemented locations, read as `0'. Shaded cells are not used by Timer0. Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read `0'.
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NOTES:
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11.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR1H and TMR1L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt on overflow * Module Reset on CCP Special Event Trigger * Device clock status flag (T1RUN) A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module's operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. Timer1 is controlled through the T1CON Control register (Register 11-1). It also contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>).
REGISTER 11-1:
R/W-0 RD16 bit 7 Legend: R = Readable bit -n = Value at POR bit 7
T1CON: TIMER1 CONTROL REGISTER
R-0 T1RUN R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from RC0/T1OSO/T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
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11.1 Timer1 Operation
Timer1 can operate in one of these modes: * Timer * Synchronous Counter * Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. When Timer1 is enabled, the RC1/T1OSI/UOE and RC0/T1OSO/T1CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as `0'.
FIGURE 11-1:
TIMER1 BLOCK DIAGRAM
Timer1 Oscillator On/Off 1 Prescaler 1, 2, 4, 8 0 2 T1OSCEN(1) T1CKPS1:T1CKPS0 T1SYNC TMR1ON Sleep Input TMR1CS Timer1 On/Off Synchronize Detect 0
T1OSO/T1CKI FOSC/4 Internal Clock
1
T1OSI
Clear TMR1 (CCP Special Event Trigger)
TMR1L
TMR1 High Byte
Set TMR1IF on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 11-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator 1
T1OSO/T1CKI FOSC/4 Internal Clock TMR1CS T1OSCEN T1CKPS1:T1CKPS0 T1SYNC TMR1ON
(1)
1 Prescaler 1, 2, 4, 8 0 2
Synchronize Detect 0
T1OSI
Sleep Input
Timer1 On/Off
Clear TMR1 (CCP Special Event Trigger)
TMR1L
TMR1 High Byte 8
Set TMR1IF on Overflow
Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
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11.2 Timer1 16-Bit Read/Write Mode
TABLE 11-1:
Osc Type LP Timer1 can be configured for 16-bit reads and writes (see Figure 11-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L.
CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4)
Freq 32 kHz C1 27 pF
(1)
C2 27 pF(1)
Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only.
11.3.1
USING TIMER1 AS A CLOCK SOURCE
11.3
Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting the Timer1 Oscillator Enable bit, T1OSCEN (T1CON<3>). The oscillator is a low-power circuit rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is shown in Figure 11-3. Table 11-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator.
The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select bits, SCS1:SCS0 (OSCCON<1:0>), to `01', the device switches to SEC_RUN mode. Both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 3.0 "Power-Managed Modes". Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN (T1CON<6>), is set. This can be used to determine the controller's current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source.
FIGURE 11-3:
EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR
PIC18FXXXX
T1OSI XTAL 32.768 kHz T1OSO
C1 33 pF
11.3.2
LOW-POWER TIMER1 OPTION
C2 33 pF Note: See the Notes with Table 11-1 for additional information about capacitor selection.
The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. When the LPT1OSC Configuration bit is set, the Timer1 oscillator operates in a low-power mode. When LPT1OSC is not set, Timer1 operates at a higher power level. Power consumption for a particular mode is relatively constant, regardless of the device's operating mode. The default Timer1 configuration is the higher power mode. As the low-power Timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration.
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11.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS
11.5
Resetting Timer1 Using the CCP Special Event Trigger
The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 11-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 11-4, may be helpful when used on a single-sided PCB or in addition to a ground plane.
If the CCP module is configured in Compare mode to generate a Special Event Trigger (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. The trigger from CCP1 will also start an A/D conversion if the A/D module is enabled (see Section 13.3.4 "Special Event Trigger" for more information). The module must be configured as either a timer or a synchronous counter to take advantage of this feature. When used this way, the CCPRH:CCPRL register pair effectively becomes a period register for Timer1. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take precedence. Note: The Special Event Triggers from the CCP1 module will not set the TMR1IF interrupt flag bit (PIR1<0>).
FIGURE 11-4:
OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING
VDD VSS OSC1 OSC2
11.6
Using Timer1 as a Real-Time Clock
RC0 RC1
RC2 Note: Not drawn to scale.
Adding an external LP oscillator to Timer1 (such as the one described in Section 11.3 "Timer1 Oscillator") gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 11-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine which increments the seconds counter by one. Additional counters for minutes and hours are incremented as the previous counter overflows. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1) as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times.
11.4
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>).
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EXAMPLE 11-1:
RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN RTCisr BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F d'59' secs secs mins, F d'59' mins mins hours, F d'23' hours d'01' hours ; ; ; ; ; ; ; ; ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? No, done Clear seconds Increment minutes 60 minutes elapsed? No, done clear minutes Increment hours 24 hours elapsed? 80h TMR1H TMR1L b'00001111' T1OSC secs mins d'12' hours PIE1, TMR1IE ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ;
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
; Enable Timer1 interrupt
; No, done ; Reset hours to 1 ; Done
TABLE 11-2:
Name INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE -- -- -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Reset Values on page 49 51 51 51 50 50 TMR1CS TMR1ON 50
GIE/GIEH PEIE/GIEL -- -- -- ADIF ADIE ADIP
Timer1 Register Low Byte TImer1 Register High Byte RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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12.0 TIMER2 MODULE
12.1 Timer2 Operation
The Timer2 module timer incorporates the following features: * 8-bit timer and period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4 and 1:16) * Software programmable postscaler (1:1 through 1:16) * Interrupt on TMR2 to PR2 match The module is controlled through the T2CON register (Register 12-1) which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. A simplified block diagram of the module is shown in Figure 12-1. In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 2-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The value of TMR2 is compared to that of the period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/ postscaler (see Section 12.2 "Timer2 Interrupt"). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: * a write to the TMR2 register * a write to the T2CON register * any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written.
REGISTER 12-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3
T2CON: TIMER2 CONTROL REGISTER
R/W-0 R/W-0 T2OUTPS2 R/W-0 T2OUTPS1 R/W-0 T2OUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0
T2OUTPS3
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
bit 2
bit 1-0
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12.2 Timer2 Interrupt
Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/ postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
12.3
TMR2 Output
The unscaled output of TMR2 is available primarily to the CCP module, where it is used as a time base for operations in PWM mode.
FIGURE 12-1:
TIMER2 BLOCK DIAGRAM
4 1:1 to 1:16 Postscaler
T2OUTPS3:T2OUTPS0 2 T2CKPS1:T2CKPS0
Reset
Set TMR2IF TMR2 Output (to PWM)
TMR2/PR2 Match
FOSC/4
1:1, 1:4, 1:16 Prescaler
TMR2
8
Comparator 8
PR2
8
Internal Data Bus
TABLE 12-1:
Name Bit 7
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE -- -- -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Reset Values on page 49 51 51 51 50 50 50
INTCON GIE/GIEH PEIE/GIEL PIR1 PIE1 IPR1 TMR2 T2CON PR2 -- -- -- -- ADIF ADIE ADIP
Timer2 Register T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 Timer2 Period Register
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module.
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13.0 CAPTURE/COMPARE/PWM (CCP) MODULE
PIC18F2450/4450 devices have one CCP (Capture/ Compare/PWM) module. The module contains a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
REGISTER 13-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4
CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER
U-0 -- R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' DC1B1:DC1B0: PWM Duty Cycle for CCP Module bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. CCP1M3:CCP1M0: CCP Module Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCP module) 0001 = Reserved 0010 = Compare mode: toggle output on match (CCP1IF bit is set) 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize CCP1 pin low; on compare match, force CCP1 pin high (CCP1IF bit is set) 1001 = Compare mode: initialize CCP1 pin high; on compare match, force CCP1 pin low (CCP1IF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCP1IF bit is set, CCP1 pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer and start A/D conversion on CCP1 match (CCP1IF bit is set) 11xx = PWM mode
bit 3-0
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13.1 CCP Module Configuration
13.2.1 CCP1 PIN CONFIGURATION
The Capture/Compare/PWM module is associated with a control register (generically, CCP1CON) and a data register (CCPR1). The data register, in turn, is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). All registers are both readable and writable. In Capture mode, the CCP1 pin should be configured as an input by setting the corresponding TRIS direction bit. Note: If RC2/CCP1 is configured as an output, a write to the port can cause a capture condition.
13.1.1
CCP MODULE AND TIMER RESOURCES
13.2.2
SOFTWARE INTERRUPT
The CCP module utilizes Timer1 or Timer2, depending on the mode selected. Timer1 is available to the module in Capture or Compare modes, while Timer2 is available for modules in PWM mode.
TABLE 13-1:
CCP MODE - TIMER RESOURCE
Timer Resource Timer1 Timer1 Timer2
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCP1IF, should also be cleared following any such change in operating mode.
13.2.3
CCP PRESCALER
CCP Mode Capture Compare PWM
In Timer1 in Asynchronous Counter mode, the capture operation will not work.
There are four prescaler settings in Capture mode. They are specified as part of the operating mode selected by the mode select bits (CCP1M3:CCP1M0). Whenever the CCP module is turned off or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 13-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
13.2
Capture Mode
In Capture mode, the CCPR1H:CCPR1L register pair captures the 16-bit value of the TMR1 register when an event occurs on the corresponding CCP1 pin. An event is defined as one of the following: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge
EXAMPLE 13-1:
CHANGING BETWEEN CAPTURE PRESCALERS (CCP1 SHOWN)
; ; ; ; ; ; Turn CCP module off Load WREG with the new prescaler mode value and CCP ON Load CCP1CON with this value
The event is selected by the mode select bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF, is set; it must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.
CLRF MOVLW
CCP1CON NEW_CAPT_PS
MOVWF
CCP1CON
FIGURE 13-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set CCP1IF
CCP1 pin Prescaler / 1, 4, 16 and Edge Detect CCPR1H TMR1 Enable CCP1CON<3:0> Q1:Q4 4 4 TMR1H TMR1L CCPR1L
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13.3 Compare Mode
13.3.3 SOFTWARE INTERRUPT MODE
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 pin can be: * * * * driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the I/O latch) When the Generate Software Interrupt mode is chosen (CCP1M3:CCP1M0 = 1010), the CCP1 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP1IE bit is set.
13.3.4
SPECIAL EVENT TRIGGER
The action on the pin is based on the value of the mode select bits (CCP1M3:CCP1M0). At the same time, the interrupt flag bit, CCP1IF, is set.
The CCP module is equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode (CCP1M3:CCP1M0 = 1011). For the CCP module, the Special Event Trigger resets the Timer1 register pair. This allows the CCPR1 registers to serve as a programmable period register for the Timer1. The Special Event Trigger for CCP1 can also start an A/D conversion. In order to do this, the A/D converter must already be enabled.
13.3.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by clearing the appropriate TRIS bit. Note: Clearing the CCP1CON register will force the RC2 compare output latch to the default low level.
13.3.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
FIGURE 13-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger (Timer1 Reset) CCP1 pin Comparator Compare Match Output Logic 4 CCP1CON<3:0> TMR1H TMR1L S R TRIS Output Enable Q
CCPR1H
CCPR1L
Set CCP1IF
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TABLE 13-2:
Name INTCON RCON PIR1 PIE1 IPR1 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1
Bit 7 Bit 6 Bit 5 TMR0IE -- RCIF RCIE RCIP -- Bit 4 INT0IE RI TXIF TXIE TXIP -- Bit 3 RBIE TO -- -- -- -- Bit 2 TMR0IF PD CCP1IF CCP1IE CCP1IP TRISC2 Bit 1 INT0IF POR TMR2IF TMR2IE TMR2IP TRISC1 Bit 0 RBIF BOR TMR1IF TMR1IE TMR1IP TRISC0 Reset Values on page 49 50 51 51 51 51 50 50 TMR1CS TMR1ON 50 50 50 CCP1M3 CCP1M2 CCP1M1 CCP1M0 50
GIE/GIEH PEIE/GIEL IPEN -- -- -- TRISC7 SBOREN ADIF ADIE ADIP TRISC6
(1)
Timer1 Register Low Byte Timer1 Register High Byte RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte -- -- DC1B1 DC1B0
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by Capture/Compare and Timer1. Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as `0'.
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13.4 PWM Mode
13.4.1 PWM PERIOD
In Pulse-Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Figure 13-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 13.4.3 "Setup for PWM Operation". The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
EQUATION 13-1:
PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note:
FIGURE 13-3:
Duty Cycle Registers CCPR1L
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
CCPR1H (Slave)
Comparator
R
Q CCP1 Output
TMR2
(Note 1) S
The Timer2 postscalers (see Section 12.0 "Timer2 Module") are not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Comparator Clear Timer, CCP1 pin and latch D.C.
Corresponding TRIS bit
13.4.2
PWM DUTY CYCLE
PR2
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
A PWM output (Figure 13-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> bits contain the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time:
EQUATION 13-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.
FIGURE 13-4:
Period
PWM OUTPUT
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
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The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation:
13.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the appropriate TRIS bit. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. Configure the CCP module for PWM operation.
EQUATION 13-3:
FOSC log --------------- FPWM PWM Resolution (max) = -----------------------------bits log ( 2 ) Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
TABLE 13-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
2.44 kHz 16 FFh 10 9.77 kHz 4 FFh 10 39.06 kHz 1 FFh 10 156.25 kHz 1 3Fh 8 312.50 kHz 1 1Fh 7 416.67 kHz 1 17h 6.58
PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 13-4:
Name INTCON RCON PIR1 PIE1 IPR1 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 Bit 6 Bit 5 TMR0IE -- RCIF RCIE RCIP -- Bit 4 INT0IE RI TXIF TXIE TXIP -- Bit 3 RBIE TO -- -- -- -- Bit 2 TMR0IF PD CCP1IF CCP1IE CCP1IP TRISC2 Bit 1 INT0IF POR TMR2IF TMR2IE TMR2IP TRISC1 Bit 0 RBIF BOR TMR1IF TMR1IE TMR1IP TRISC0 Reset Values on page 49 50 51 51 51 51 50 50 T2CKPS1 T2CKPS0 50 50 50 CCP1M3 CCP1M2 CCP1M1 CCP1M0 50
GIE/GIEH PEIE/GIEL IPEN -- -- -- TRISC7 SBOREN(1) ADIF ADIE ADIP TRISC6
Timer2 Register Timer2 Period Register -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte -- -- DC1B1 DC1B0
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PWM or Timer2. Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as `0'.
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14.0 UNIVERSAL SERIAL BUS (USB)
any USB host and the PIC(R) microcontroller. The SIE can be interfaced directly to the USB, utilizing the internal transceiver, or it can be connected through an external transceiver. An internal 3.3V regulator is also available to power the internal transceiver in 5V applications. Some special hardware features have been included to improve performance. Dual port memory in the device's data memory space (USB RAM) has been supplied to share direct memory access between the microcontroller core and the SIE. Buffer descriptors are also provided, allowing users to freely program endpoint memory usage within the USB RAM space. Figure 14-1 presents a general overview of the USB peripheral and its features.
This section describes the details of the USB peripheral. Because of the very specific nature of the module, knowledge of USB is expected. Some high-level USB information is provided in Section 14.9 "Overview of USB" only for application design reference. Designers are encouraged to refer to the official specification published by the USB Implementers Forum (USB-IF) for the latest information. USB Specification Revision 2.0 is the most current specification at the time of publication of this document.
14.1
Overview of the USB Peripheral
The PIC18F2450/4450 device family contains a fullspeed and low-speed compatible USB Serial Interface Engine (SIE) that allows fast communication between
FIGURE 14-1:
USB PERIPHERAL AND OPTIONS
PIC18F2450/4450 Family
3.3V Regulator VREGEN EN
VUSB
External 3.3V Supply(3)
External Pull-ups(2) FSEN UTRDIS USB Clock from the Oscillator Module Transceiver FS OE D+ DUOE(1) VM(1) VP(1) RCV(1) VMO(1) VPO(1) External Transceiver USB Bus (Full Speed) (Low Speed) USB Bus
USB Control and Configuration USB SIE
256-Byte USB RAM
Note 1: 2: 3:
This signal is only available if the internal transceiver is disabled (UTRDIS = 1). The pull-ups can be supplied either from the VUSB pin or from an external 3.3V supply. Do not enable the internal regulator when using an external 3.3V supply.
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14.2 USB Status and Control
The operation of the USB module is configured and managed through three control registers. In addition, a total of 22 registers are used to manage the actual USB transactions. The registers are: * * * * * * USB Control register (UCON) USB Configuration register (UCFG) USB Transfer Status register (USTAT) USB Device Address register (UADDR) Frame Number registers (UFRMH:UFRML) Endpoint Enable registers 0 through 15 (UEPn) In addition, the USB Control register contains a status bit, SE0 (UCON<5>), which is used to indicate the occurrence of a single-ended zero on the bus. When the USB module is enabled, this bit should be monitored to determine whether the differential data lines have come out of a single-ended zero condition. This helps to differentiate the initial power-up state from the USB Reset signal. The overall operation of the USB module is controlled by the USBEN bit (UCON<3>). Setting this bit activates the module and resets all of the PPBI bits in the Buffer Descriptor Table to `0'. This bit also activates the onchip voltage regulator, if enabled. Thus, this bit can be used as a soft attach/detach to the USB. Although all status and control bits are ignored when this bit is clear, the module needs to be fully preconfigured prior to setting this bit.
14.2.1
USB CONTROL REGISTER (UCON)
The USB Control register (Register 14-1) contains bits needed to control the module behavior during transfers. The register contains bits that control the following: * * * * Main USB Peripheral Enable Ping-Pong Buffer Pointer Reset Control of the Suspend mode Packet Transfer Disable
REGISTER 14-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
UCON: USB CONTROL REGISTER
R/W-0 R-x SE0 R/C-0 PKTDIS R/W-0 USBEN R/W-0 RESUME R/W-0 SUSPND U-0 -- bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PPBRST
Unimplemented: Read as `0' PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks 0 = Ping-Pong Buffer Pointers not being reset SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing disabled, automatically set when a SETUP token is received 0 = SIE token and packet processing enabled USBEN: USB Module Enable bit 1 = USB module and supporting circuitry enabled (device attached) 0 = USB module and supporting circuitry disabled (device detached) RESUME: Resume Signaling Enable bit 1 = Resume signaling activated 0 = Resume signaling disabled SUSPND: Suspend USB bit 1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive 0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate Unimplemented: Read as `0'
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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The PPBRST bit (UCON<6>) controls the Reset status when Double-Buffering mode (ping-pong buffering) is used. When the PPBRST bit is set, all Ping-Pong Buffer Pointers are set to the Even buffers. PPBRST has to be cleared by firmware. This bit is ignored in buffering modes not using ping-pong buffering. The PKTDIS bit (UCON<4>) is a flag indicating that the SIE has disabled packet transmission and reception. This bit is set by the SIE when a SETUP token is received to allow setup processing. This bit cannot be set by the microcontroller, only cleared; clearing it allows the SIE to continue transmission and/or reception. Any pending events within the Buffer Descriptor Table will still be available, indicated within the USTAT register's FIFO buffer. The RESUME bit (UCON<2>) allows the peripheral to perform a remote wake-up by executing Resume signaling. To generate a valid remote wake-up, firmware must set RESUME for 10 ms and then clear the bit. For more information on Resume signaling, see Sections 7.1.7.5, 11.4.4 and 11.9 in the USB 2.0 specification. The SUSPND bit (UCON<1>) places the module and supporting circuitry (i.e., voltage regulator) in a lowpower mode. The input clock to the SIE is also disabled. This bit should be set by the software in response to an IDLEIF interrupt. It should be reset by the microcontroller firmware after an ACTVIF interrupt is observed. When this bit is active, the device remains attached to the bus but the transceiver outputs remain Idle. The voltage on the VUSB pin may vary depending on the value of this bit. Setting this bit before a IDLEIF request will result in unpredictable bus behavior. Note: While in Suspend mode, a typical bus powered USB device is limited to 500 A of current. This is the complete current drawn by the PICmicro device and its supporting circuitry. Care should be taken to assure minimum current draw when the device enters Suspend mode. The UCFG register also contains two bits which aid in module testing, debugging and USB certifications. These bits control output enable state monitoring and eye pattern generation. Note: The USB speed, transceiver and pull-up should only be configured during the module setup phase. It is not recommended to switch these settings while the module is enabled.
14.2.2.1
Internal Transceiver
The USB peripheral has a built-in, USB 2.0, full-speed and low-speed compliant transceiver, internally connected to the SIE. This feature is useful for low-cost single chip applications. The UTRDIS bit (UCFG<3>) controls the transceiver; it is enabled by default (UTRDIS = 0). The FSEN bit (UCFG<2>) controls the transceiver speed; setting the bit enables full-speed operation. The USB specification requires 3.3V operation for communications; however, the rest of the chip may be running at a higher voltage. Thus, the transceiver is supplied power from a separate source, VUSB.
14.2.2.2
External Transceiver
This module provides support for use with an off-chip transceiver. The off-chip transceiver is intended for applications where physical conditions dictate the location of the transceiver to be away from the SIE. For example, applications that require isolation from the USB could use an external transceiver through some isolation to the microcontroller's SIE (Figure 14-2). External transceiver operation is enabled by setting the UTRDIS bit.
FIGURE 14-2:
TYPICAL EXTERNAL TRANSCEIVER WITH ISOLATION
VDD Isolated from USB 3.3V Derived from USB
PIC(R) Microcontroller
VDD VUSB VM VP RCV VMO VPO UOE
14.2.2
USB CONFIGURATION REGISTER (UCFG)
1.5 k Isolation Transceiver D+ D-
Prior to communicating over USB, the module's associated internal and/or external hardware must be configured. Most of the configuration is performed with the UCFG register (Register 14-2). The separate USB voltage regulator (see Section 14.2.2.7 "Internal Regulator") is controlled through the Configuration registers. The UFCG register contains most of the bits that control the system level behavior of the USB module. These include: * Bus Speed (full speed versus low speed) * On-Chip Transceiver Enable * Ping-Pong Buffer Usage
Note:
The above setting shows a simplified schematic for a full-speed configuration using an external transceiver with isolation.
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REGISTER 14-2:
R/W-0 UTEYE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
UCFG: USB CONFIGURATION REGISTER
R/W-0 U-0 -- R/W-0 UPUEN(2,3) R/W-0 UTRDIS(2) R/W-0 FSEN(2) R/W-0 PPB1 R/W-0 PPB0 bit 0
UOEMON(1)
UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled UOEMON: USB OE Monitor Enable bit(1) 1 = UOE signal active; it indicates intervals during which the D+/D- lines are driving 0 = UOE signal inactive Unimplemented: Read as `0' UPUEN: USB On-Chip Pull-up Enable bit(2,3) 1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0) 0 = On-chip pull-up disabled UTRDIS: On-Chip Transceiver Disable bit(2) 1 = On-chip transceiver disabled; digital transceiver interface enabled 0 = On-chip transceiver active FSEN: Full-Speed Enable bit(2) 1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz 0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz PPB1:PPB0: Ping-Pong Buffers Configuration bits 11 = Enabled for all endpoints except Endpoint 0 10 = Even/Odd ping-pong buffers enabled for all endpoints 01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0 00 = Even/Odd ping-pong buffers disabled If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting. The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These values must be preconfigured prior to enabling the module. This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored. The VPO and VMO signals are outputs from the SIE to the external transceiver. The RCV signal is the output from the external transceiver to the SIE; it represents the differential signals from the serial bus translated into a single pulse train. The VM and VP signals are used to report conditions on the serial bus to the SIE that can't be captured with the RCV signal. The combinations of states of these signals and their interpretation are listed in Table 14-1 and Table 14-2.
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1-0
Note 1: 2: 3:
There are 6 signals from the module to communicate with and control an external transceiver: * * * * * * VM: Input from the single-ended D- line VP: Input from the single-ended D+ line RCV: Input from the differential receiver VMO: Output to the differential line driver VPO: Output to the differential line driver UOE: Output enable
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TABLE 14-1:
VPO 0 0 1 1 VMO 0 1 0 1
DIFFERENTIAL OUTPUTS TO TRANSCEIVER
Bus State Single-Ended Zero Differential `0' Differential `1' Illegal Condition
14.2.2.5
USB Output Enable Monitor
The USB OE monitor provides indication as to whether the SIE is listening to the bus or actively driving the bus. This is enabled by default when using an external transceiver or when UCFG<6> = 1. The USB OE monitoring is useful for initial system debugging, as well as scope triggering during eye pattern generation tests.
14.2.2.6 TABLE 14-2:
VP 0 0 1 1 VM 0 1 0 1
Eye Pattern Test Enable
SINGLE-ENDED INPUTS FROM TRANSCEIVER
Bus State Single-Ended Zero Low Speed High Speed Error
An automatic eye pattern test can be generated by the module when the UCFG<7> bit is set. The eye pattern output will be observable based on module settings, meaning that the user is first responsible for configuring the SIE clock settings, pull-up resistor and Transceiver mode. In addition, the module has to be enabled. Once UTEYE is set, the module emulates a switch from a receive to transmit state and will start transmitting a J-K-J-K bit sequence (K-J-K-J for full speed). The sequence will be repeated indefinitely while the Eye Pattern Test mode is enabled. Note that this bit should never be set while the module is connected to an actual USB system. This test mode is intended for board verification to aid with USB certification tests. It is intended to show a system developer the noise integrity of the USB signals which can be affected by board traces, impedance mismatches and proximity to other system components. It does not properly test the transition from a receive to a transmit state. Although the eye pattern is not meant to replace the more complex USB certification test, it should aid during first order system debugging.
The UOE signal toggles the state of the external transceiver. This line is pulled low by the device to enable the transmission of data from the SIE to an external device.
14.2.2.3
Pull-up Resistors
The PIC18F2450/4450 devices require an external pullup resistor to meet the requirements for low-speed and full-speed USB. Either an external 3.3V supply or the VUSB pin may be used to pull up D+ or D-. The pull-up resistor must be 1.5 k (5%) as required by the USB specifications. Figure 14-3 shows an example with the VUSB pin.
FIGURE 14-3:
PIC Microcontroller
(R)
EXTERNAL CIRCUITRY
Host Controller/HUB
14.2.2.7
Internal Regulator
VUSB
The PIC18F2450/4450 devices have a built-in 3.3V regulator to provide power to the internal transceiver and provide a source for the external pull-ups. An external 220 nF (20%) capacitor is required for stability. Note: The drive from VUSB is sufficient to only drive an external pull-up in addition to the internal transceiver.
1.5 k D+ D-
Note:
The above setting shows a typical connection for a full-speed configuration using an on-chip regulator and an external pull-up resistor.
The regulator is enabled by default and can be disabled through the VREGEN Configuration bit. When enabled, the voltage is visible on pin VUSB. When the regulator is disabled, a 3.3V source must be provided through the VUSB pin for the internal transceiver. If the internal transceiver is disabled, VUSB is not used. Note 1: Do not enable the internal regulator if an external regulator is connected to VUSB. 2: VDD must be greater than VUSB at all times, even with the regulator disabled.
14.2.2.4
Ping-Pong Buffer Configuration
The usage of ping-pong buffers is configured using the PPB1:PPB0 bits. Refer to Section 14.4.4 "Ping-Pong Buffering" for a complete explanation of the ping-pong buffers.
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14.2.3 USB STATUS REGISTER (USTAT)
The USB Status register reports the transaction status within the SIE. When the SIE issues a USB transfer complete interrupt, USTAT should be read to determine the status of the transfer. USTAT contains the transfer endpoint number, direction and Ping-Pong Buffer Pointer value (if used). Note: The data in the USB Status register is valid only when the TRNIF interrupt flag is asserted. Clearing the transfer complete flag bit, TRNIF, causes the SIE to advance the FIFO. If the next data in the FIFO holding register is valid, the SIE will immediately reassert the interrupt. If no additional data is present, TRNIF will remain clear; USTAT data will no longer be reliable. Note: If an endpoint request is received while the USTAT FIFO is full, the SIE will automatically issue a NAK back to the host.
The USTAT register is actually a read window into a four-byte status FIFO, maintained by the SIE. It allows the microcontroller to process one transfer while the SIE processes additional endpoints (Figure 14-4). When the SIE completes using a buffer for reading or writing data, it updates the USTAT register. If another USB transfer is performed before a transaction complete interrupt is serviced, the SIE will store the status of the next transfer into the status FIFO.
FIGURE 14-4:
USTAT FIFO
USTAT from SIE
4-byte FIFO for USTAT
Clearing TRNIF Advances FIFO
Data Bus
REGISTER 14-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3
USTAT: USB STATUS REGISTER
R-x R-x ENDP2 R-x ENDP1 R-x ENDP0 R-x DIR R-x PPBI(1) U-0 -- bit 0
ENDP3
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits (represents the number of the BDT updated by the last USB transfer) 1111 = Endpoint 15 1110 = Endpoint 14 .... 0001 = Endpoint 1 0000 = Endpoint 0 DIR: Last BD Direction Indicator bit 1 = The last transaction was an IN token 0 = The last transaction was an OUT or SETUP token PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the Odd BD bank 0 = The last transaction was to the Even BD bank Unimplemented: Read as `0' This bit is only valid for endpoints with available Even and Odd BD registers.
bit 2
bit 1
bit 0 Note 1:
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14.2.4 USB ENDPOINT CONTROL
Each of the 16 possible bidirectional endpoints has its own independent control register, UEPn (where `n' represents the endpoint number). Each register has an identical complement of control bits. The prototype is shown in Register 14-4. The EPHSHK bit (UEPn<4>) controls handshaking for the endpoint; setting this bit enables USB handshaking. Typically, this bit is always set except when using isochronous endpoints. The EPCONDIS bit (UEPn<3>) is used to enable or disable USB control operations (SETUP) through the endpoint. Clearing this bit enables SETUP transactions. Note that the corresponding EPINEN and EPOUTEN bits must be set to enable IN and OUT transactions. For Endpoint 0, this bit should always be cleared since the USB specifications identify Endpoint 0 as the default control endpoint. The EPOUTEN bit (UEPn<2>) is used to enable or disable USB OUT transactions from the host. Setting this bit enables OUT transactions. Similarly, the EPINEN bit (UEPn<1>) enables or disables USB IN transactions from the host. The EPSTALL bit (UEPn<0>) is used to indicate a STALL condition for the endpoint. If a STALL is issued on a particular endpoint, the EPSTALL bit for that endpoint pair will be set by the SIE. This bit remains set until it is cleared through firmware, or until the SIE is reset.
REGISTER 14-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
U-0 -- U-0 -- R/W-0 EPHSHK R/W-0 EPCONDIS R/W-0 EPOUTEN R/W-0 EPINEN R/W-0 EPSTALL(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake enabled 0 = Endpoint handshake disabled (typically used for isochronous endpoints) EPCONDIS: Bidirectional Endpoint Control bit If EPOUTEN = 1 and EPINEN = 1: 1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed 0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed EPOUTEN: Endpoint Output Enable bit 1 = Endpoint n output enabled 0 = Endpoint n output disabled EPINEN: Endpoint Input Enable bit 1 = Endpoint n input enabled 0 = Endpoint n input disabled EPSTALL: Endpoint Stall Enable bit(1) 1 = Endpoint n is stalled 0 = Endpoint n is not stalled Valid only if Endpoint n is enabled; otherwise, the bit is ignored.
bit 3
bit 2
bit 1
bit 0
Note 1:
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14.2.5 USB ADDRESS REGISTER (UADDR) FIGURE 14-5:
The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written by the microcontroller during the USB setup phase (enumeration) as part of the Microchip USB firmware support.
IMPLEMENTATION OF USB RAM IN DATA MEMORY SPACE
000h User Data 1FFh 200h Unused Buffer Descriptors, USB Data or User Data 3FFh 400h 4FFh 500h
Banks 0 to 1 Banks 2 to 3 Bank 4
14.2.6
USB FRAME NUMBER REGISTERS (UFRMH:UFRML)
The Frame Number registers contain the 11-bit frame number. The low-order byte is contained in UFRML, while the three high-order bits are contained in UFRMH. The register pair is updated with the current frame number whenever a SOF token is received. For the microcontroller, these registers are read-only. The Frame Number register is primarily used for isochronous transfers.
USB Data or User Data
14.3
USB RAM
Banks 5 to 14
7FFh 800h Unused
USB data moves between the microcontroller core and the SIE through a memory space known as the USB RAM. This is a special dual port memory that is mapped into the normal data memory space in Bank 4 (400h to 4FFh) for a total of 256 bytes (Figure 14-5). Some portion of Bank 4 (400h through 4FFh) is used specifically for endpoint buffer control, while the remaining portion is available for USB data. Depending on the type of buffering being used, all but 8 bytes of Bank 4 may also be available for use as USB buffer space. Although USB RAM is available to the microcontroller as data memory, the sections that are being accessed by the SIE should not be accessed by the microcontroller. A semaphore mechanism is used to determine the access to a particular buffer at any given time. This is discussed in Section 14.4.1.1 "Buffer Ownership".
Bank15
SFRs
F00h F80h FFFh
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14.4 Buffer Descriptors and the Buffer Descriptor Table
14.4.1 BD STATUS AND CONFIGURATION
Buffer descriptors not only define the size of an endpoint buffer, but also determine its configuration and control. Most of the configuration is done with the BD Status register, BDnSTAT. Each BD has its own unique and correspondingly numbered BDnSTAT register.
The registers in Bank 4 are used specifically for endpoint buffer control in a structure known as the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configuration. The BDT is composed of Buffer Descriptors (BD) which are used to define and control the actual buffers in the USB RAM space. Each BD, in turn, consists of four registers, where n represents one of the 64 possible BDs (range of 0 to 63): * * * * BDnSTAT: BD Status register BDnCNT: BD Byte Count register BDnADRL: BD Address Low register BDnADRH: BD Address High register
FIGURE 14-6:
Address 400h Buffer Descriptor 401h 402h 403h 480h
EXAMPLE OF A BUFFER DESCRIPTOR
Registers BD0STAT BD0CNT BD0ADRL BD0ADRH (xxh) 10h 80h 04h Size of Block Starting Address Contents
BDs always occur as a four-byte block in the sequence, BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address of BDnSTAT is always an offset of (4n - 1) (in hexadecimal) from 400h, with n being the buffer descriptor number. Depending on the buffering configuration used (Section 14.4.4 "Ping-Pong Buffering"), there are up to 32, 33 or 64 sets of buffer descriptors. At a minimum, the BDT must be at least 8 bytes long. This is because the USB specification mandates that every device must have Endpoint 0 with both input and output for initial setup. Depending on the endpoint and buffering configuration, the BDT can be as long as 256 bytes. Although they can be thought of as Special Function Registers, the Buffer Descriptor Status and Address registers are not hardware mapped, as conventional microcontroller SFRs in Bank 15 are. If the endpoint corresponding to a particular BD is not enabled, its registers are not used. Instead of appearing as unimplemented addresses, however, they appear as available RAM. Only when an endpoint is enabled by setting the UEPn<1> bit does the memory at those addresses become functional as BD registers. As with any address in the data memory space, the BD registers have an indeterminate value on any device Reset. A total of 256 bytes of address space in Bank 4 is available for BDT and USB data RAM. In Ping-Pong Buffer mode, all the 16 bidirectional endpoints can not be implemented where BDT itself can be as long as 256 bytes. In the majority of USB applications, few endpoints are required to be implemented. Hence, a small portion of the 256 bytes will be used for BDT and the rest can be used for USB data. An example of a BD for a 16-byte buffer, starting at 480h, is shown in Figure 14-6. A particular set of BD registers is only valid if the corresponding endpoint has been enabled using the UEPn register. All BD registers are available in USB RAM. The BD for each endpoint should be set up prior to enabling the endpoint.
Buffer
USB Data
48Fh Note: Memory regions not to scale.
Unlike other control registers, the bit configuration for the BDnSTAT register is context sensitive. There are two distinct configurations, depending on whether the microcontroller or the USB module is modifying the BD and buffer at a particular time. Only three bit definitions are shared between the two.
14.4.1.1
Buffer Ownership
Because the buffers and their BDs are shared between the CPU and the USB module, a simple semaphore mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory. This is done by using the UOWN bit (BDnSTAT<7>) as a semaphore to distinguish which is allowed to update the BD and associated buffers in memory. UOWN is the only bit that is shared between the two configurations of BDnSTAT. When UOWN is clear, the BD entry is "owned" by the microcontroller core. When the UOWN bit is set, the BD entry and the buffer memory are "owned" by the USB peripheral. The core should not modify the BD or its corresponding data buffer during this time. Note that the microcontroller core can still read BDnSTAT while the SIE owns the buffer and vice versa. The buffer descriptors have a different meaning based on the source of the register update. Prior to placing ownership with the USB peripheral, the user can configure the basic operation of the peripheral through the BDnSTAT bits. During this time, the byte count and buffer location registers can also be set.
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When UOWN is set, the user can no longer depend on the values that were written to the BDs. From this point, the SIE updates the BDs as necessary, overwriting the original BD values. The BDnSTAT register is updated by the SIE with the token PID and the transfer count, BDnCNT, is updated. The BDnSTAT byte of the BDT should always be the last byte updated when preparing to arm an endpoint. The SIE will clear the UOWN bit when a transaction has completed. The only exception to this is when KEN is enabled and/or BSTALL is enabled. No hardware mechanism exists to block access when the UOWN bit is set. Thus, unexpected behavior can occur if the microcontroller attempts to modify memory when the SIE owns it. Similarly, reading such memory may produce inaccurate data until the USB peripheral returns ownership to the microcontroller. the USB RAM and the USB transfer complete interrupt flag will not be set. The SIE will send an ACK token back to the host to Acknowledge receipt, however. The effects of the DTSEN bit on the SIE are summarized in Table 14-3. The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides support for control transfers, usually one-time stalls on Endpoint 0. It also provides support for the SET_FEATURE/CLEAR_FEATURE commands specified in Chapter 9 of the USB specification; typically, continuous STALLs to any endpoint other than the default control endpoint. The BSTALL bit enables buffer stalls. Setting BSTALL causes the SIE to return a STALL token to the host if a received token would use the BD in that location. The EPSTALL bit in the corresponding UEPn control register is set and a STALL interrupt is generated when a STALL is issued to the host. The UOWN bit remains set and the BDs are not changed unless a SETUP token is received. In this case, the STALL condition is cleared and the ownership of the BD is returned to the microcontroller core. The BD9:BD8 bits (BDnSTAT<1:0>) store the two most significant digits of the SIE byte count; the lower 8 digits are stored in the corresponding BDnCNT register. See Section 14.4.2 "BD Byte Count" for more information.
14.4.1.2
BDnSTAT Register (CPU Mode)
When UOWN = 0, the microcontroller core owns the BD. At this point, the other seven bits of the register take on control functions. The Data Toggle Sync Enable bit, DTSEN (BDnSTAT<3>), controls data toggle parity checking. Setting DTSEN enables data toggle synchronization by the SIE. When enabled, it checks the data packet's parity against the value of DTS (BDnSTAT<6>). If a packet arrives with an incorrect synchronization, the data will essentially be ignored. It will not be written to
TABLE 14-3:
OUT Packet from Host DATA0 DATA1 DATA0 DATA1 Either Either, with error
EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
BDnSTAT Settings DTSEN 1 1 1 1 0 x DTS 0 0 1 1 x x Handshake ACK ACK ACK ACK ACK NAK Device Response after Receiving Packet UOWN 0 1 0 1 0 1 TRNIF 1 0 1 0 1 0 BDnSTAT and USTAT Status Updated Not Updated Updated Not Updated Updated Not Updated
Legend: x = don't care
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REGISTER 14-5:
R/W-x UOWN(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
R/W-x DTS
(2)
R/W-x --
(3)
R/W-x --
(3)
R/W-x DTSEN
R/W-x BSTALL
R/W-x BC9
R/W-x BC8 bit 0
UOWN: USB Own bit(1) 0 = The microcontroller core owns the BD and its corresponding buffer DTS: Data Toggle Synchronization bit(2) 1 = Data 1 packet 0 = Data 0 packet Reserved: These bits should always be programmed to `0'(3) DTSEN: Data Toggle Synchronization Enable bit 1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored 0 = No data toggle synchronization is performed BSTALL: Buffer Stall Enable bit 1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit remains set, BD value is unchanged) 0 = Buffer stall disabled BC9:BC8: Byte Count 9 and 8 bits The byte count bits represent the number of bytes that will be transmitted for an IN token or received during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023. This bit must be initialized by the user to the desired value prior to enabling the USB module. This bit is ignored unless DTSEN = 1. If these bits are set, USB communication may not work. Hence, these bits should always be maintained as `0'.
bit 5-4 bit 3
bit 2
bit 1-0
Note 1: 2: 3:
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14.4.1.3 BDnSTAT Register (SIE Mode)
When the BD and its buffer are owned by the SIE, most of the bits in BDnSTAT take on a different meaning. The configuration is shown in Register 14-6. Once UOWN is set, any data or control settings previously written there by the user will be overwritten with data from the SIE. The BDnSTAT register is updated by the SIE with the token Packet Identifier (PID) which is stored in BDnSTAT<5:3>. The transfer count in the corresponding BDnCNT register is updated. Values that overflow the 8-bit register carry over to the two most significant digits of the count, stored in BDnSTAT<1:0>. byte count, the data packet will be rejected and a NAK handshake will be generated. When this happens, the byte count will not be updated. The 10-bit byte count is distributed over two registers. The lower 8 bits of the count reside in the BDnCNT register. The upper two bits reside in BDnSTAT<1:0>. This represents a valid byte range of 0 to 1023.
14.4.3
BD ADDRESS VALIDATION
14.4.2
BD BYTE COUNT
The BD Address register pair contains the starting RAM address location for the corresponding endpoint buffer. For an endpoint starting location to be valid, it must fall in the range of the USB RAM, 400h to 7FFh. No mechanism is available in hardware to validate the BD address. If the value of the BD address does not point to an address in the USB RAM, or if it points to an address within another endpoint's buffer, data is likely to be lost or overwritten. Similarly, overlapping a receive buffer (OUT endpoint) with a BD location in use can yield unexpected results. When developing USB applications, the user may want to consider the inclusion of software-based address validation in their code.
The byte count represents the total number of bytes that will be transmitted during an IN transfer. After an IN transfer, the SIE will return the number of bytes sent to the host. For an OUT transfer, the byte count represents the maximum number of bytes that can be received and stored in USB RAM. After an OUT transfer, the SIE will return the actual number of bytes received. If the number of bytes received exceeds the corresponding
REGISTER 14-6:
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE MICROCONTROLLER)
U-x -- R/W-x PID3 R/W-x PID2 R/W-x PID1 R/W-x PID0 R/W-x BC9 R/W-x BC8 bit 0
R/W-x UOWN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5-2 bit 1-0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
UOWN: USB Own bit 1 = The SIE owns the BD and its corresponding buffer Reserved: Not written by the SIE PID3:PID0: Packet Identifier bits The received token PID value of the last transfer (IN, OUT or SETUP transactions only). BC9:BC8: Byte Count 9 and 8 bits These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer and the actual number of bytes transmitted on an IN transfer.
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14.4.4 PING-PONG BUFFERING
An endpoint is defined to have a ping-pong buffer when it has two sets of BD entries: one set for an Even transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the other BD. Double-buffering BDs in this way allows for maximum throughput to/from the USB. The USB module supports three modes of operation: * No ping-pong support * Ping-pong buffer support for OUT Endpoint 0 only * Ping-pong buffer support for all endpoints The ping-pong buffer settings are configured using the PPB1:PPB0 bits in the UCFG register. The USB module keeps track of the Ping-Pong Pointer individually for each endpoint. All pointers are initially reset to the Even BD when the module is enabled. After the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. The Even/Odd status of the last transaction is stored in the PPBI bit of the USTAT register. The user can reset all Ping-Pong Pointers to Even using the PPBRST bit. Figure 14-7 shows the three different modes of operation and how USB RAM is filled with the BDs. BDs have a fixed relationship to a particular endpoint, depending on the buffering configuration. The mapping of BDs to endpoints is detailed in Table 14-4. This relationship also means that gaps may occur in the BDT if endpoints are not enabled contiguously. This theoretically means that the BDs for disabled endpoints could be used as buffer space. In practice, users should avoid using such spaces in the BDT unless a method of validating BD addresses is implemented.
FIGURE 14-7:
BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
PPB1:PPB0 = 01 Ping-Pong Buffer on EP0 OUT
400h EP0 OUT Descriptor EP0 IN Descriptor EP1 OUT Descriptor EP1 IN Descriptor EP0 OUT Even Descriptor EP0 OUT Odd Descriptor EP0 IN Descriptor EP1 OUT Descriptor EP1 IN Descriptor EP15 IN Descriptor EP15 IN Descriptor
PPB1:PPB0 = 00 No Ping-Pong Buffers
400h
PPB1:PPB0 = 10 Ping-Pong Buffers on all EPs
400h EP0 OUT Even Descriptor EP0 OUT Odd Descriptor EP0 IN Even Descriptor EP0 IN Odd Descriptor EP1 OUT Even Descriptor EP1 OUT Odd Descriptor EP1 IN Even Descriptor EP1 IN Odd Descriptor
47Fh
483h
Available as Data RAM
Available as Data RAM
EP15 IN Odd Descriptor 4FFh 4FFh 4FFh
Maximum Memory Used: 128 bytes Maximum BDs: 32 (BD0 to BD31) Note:
Maximum Memory Used: 132 bytes Maximum BDs: 33 (BD0 to BD32)
Maximum Memory Used: 256 bytes Maximum BDs: 64 (BD0 to BD63)
Memory area not shown to scale.
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TABLE 14-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES
BDs Assigned to Endpoint Endpoint Mode 0 (No Ping-Pong) Out 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 In 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 Mode 1 (Ping-Pong on EP0 OUT) Out 0 (E), 1 (O) 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 In 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Mode 2 (Ping-Pong on all EPs) Out 0 (E), 1 (O) 4 (E), 5 (O) 8 (E), 9 (O) 12 (E), 13 (O) 16 (E), 17 (O) 20 (E), 21 (O) 24 (E), 25 (O) 28 (E), 29 (O) 32 (E), 33 (O) 36 (E), 37 (O) 40 (E), 41 (O) 44 (E), 45 (O) 48 (E), 49 (O) 52 (E), 53 (O) 56 (E), 57 (O) 60 (E), 61 (O) In 2 (E), 3 (O) 6 (E), 7 (O) 10 (E), 11 (O) 14 (E), 15 (O) 18 (E), 19 (O) 22 (E), 23 (O) 26 (E), 27 (O) 30 (E), 31 (O) 34 (E), 35 (O) 38 (E), 39 (O) 42 (E), 43 (O) 46 (E), 47 (O) 50 (E), 51 (O) 54 (E), 55 (O) 58 (E), 59 (O) 62 (E), 63 (O)
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
TABLE 14-5:
Name BDnSTAT(1) BDnCNT(1) BDnADRL(1) BDnADRH(1) Note 1: 2:
SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
Bit 7 UOWN Byte Count Buffer Address Low Buffer Address High Bit 6 DTS(4) Bit 5 PID3(2) Bit 4 PID2(2) Bit 3 PID1(2) DTSEN(3) Bit 2 PID0(2) BSTALL(3) Bit 1 BC9 Bit 0 BC8
3: 4:
For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx). Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values written for DTSEN and BSTALL are no longer valid. Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 3 and 2 of the BDnSTAT register are used to configure the DTSEN and BSTALL settings. This bit is ignored unless DTSEN = 1.
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14.5 USB Interrupts
The USB module can generate multiple interrupt conditions. To accommodate all of these interrupt sources, the module is provided with its own interrupt logic structure, similar to that of the microcontroller. USB interrupts are enabled with one set of control registers and trapped with a separate set of flag registers. All sources are funneled into a single USB interrupt request, USBIF (PIR2<5>), in the microcontroller's interrupt logic. Figure 14-8 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts; these are enabled and flagged in the UIE and UIR registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the UEIR and UEIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level. Interrupts may be used to trap routine events in a USB transaction. Figure 14-9 shows some common events within a USB frame and their corresponding interrupts.
FIGURE 14-8:
USB INTERRUPT LOGIC FUNNEL
Second Level USB Interrupts (USB Error Conditions) Top Level USB Interrupts (USB Status Interrupts) UIR (Flag) and UIE (Enable) Registers SOFIF SOFIE TRNIF TRNIE IDLEIF IDLEIE UERRIF UERRIE STALLIF STALLIE ACTVIF ACTVIE URSTIF URSTIE USBIF
UEIR (Flag) and UEIE (Enable) Registers
BTSEF BTSEE BTOEF BTOEE DFN8EF DFN8EE CRC16EF CRC16EE CRC5EF CRC5EE PIDEF PIDEE
FIGURE 14-9:
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
From Host SETUPToken From Host From Host Data To Host Data From Host Empty Data Transaction Transaction Complete To Host ACK From Host ACK To Host ACK Set TRNIF Set TRNIF Set TRNIF
USB Reset URSTIF START-OF-FRAME SOFIF
IN Token From Host OUT Token
RESET Differential Data
SOF
SETUP
DATA
STATUS
SOF
Control Transfer(1) 1 ms Frame Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames.
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14.5.1 USB INTERRUPT STATUS REGISTER (UIR)
The USB Interrupt Status register (Register 14-7) contains the flag bits for each of the USB status interrupt sources. Each of these sources has a corresponding interrupt enable bit in the UIE register. All of the USB status flags are ORed together to generate the USBIF interrupt flag for the microcontroller's interrupt funnel. Once an interrupt bit has been set by the SIE, it must be cleared by software by writing a `0'. The flag bits can also be set in software which can aid in firmware debugging.
REGISTER 14-7:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
UIR: USB INTERRUPT STATUS REGISTER
R/W-0 SOFIF R/W-0 STALLIF R/W-0 IDLEIF
(1)
R/W-0 TRNIF
(2)
R/W-0 ACTVIF
(3)
R-0 UERRIF
(4)
R/W-0 URSTIF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' SOFIF: START-OF-FRAME Token Interrupt bit 1 = A START-OF-FRAME token received by the SIE 0 = No START-OF-FRAME token received by the SIE STALLIF: A STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the SIE 0 = A STALL handshake has not been sent IDLEIF: Idle Detect Interrupt bit(1) 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected TRNIF: Transaction Complete Interrupt bit(2) 1 = Processing of pending transaction is complete; read USTAT register for endpoint information 0 = Processing of pending transaction is not complete or no transaction is pending ACTVIF: Bus Activity Detect Interrupt bit(3) 1 = Activity on the D+/D- lines was detected 0 = No activity detected on the D+/D- lines UERRIF: USB Error Condition Interrupt bit(4) 1 = An unmasked error condition has occurred 0 = No unmasked error condition has occurred. URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset occurred; 00h is loaded into UADDR register 0 = No USB Reset has occurred Once an Idle state is detected, the user may want to place the USB module in Suspend mode. Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens). This bit is typically unmasked only following the detection of a UIDLE interrupt event. Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and cannot be set or cleared by the user.
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2: 3: 4:
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14.5.2 USB INTERRUPT ENABLE REGISTER (UIE)
The USB Interrupt Enable register (Register 14-8) contains the enable bits for the USB status interrupt sources. Setting any of these bits will enable the respective interrupt source in the UIR register. The values in this register only affect the propagation of an interrupt condition to the microcontroller's interrupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt.
REGISTER 14-8:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
UIE: USB INTERRUPT ENABLE REGISTER
R/W-0 SOFIE R/W-0 STALLIE R/W-0 IDLEIE R/W-0 TRNIE R/W-0 ACTVIE R/W-0 UERRIE R/W-0 URSTIE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' SOFIE: START-OF-FRAME Token Interrupt Enable bit 1 = START-OF-FRAME token interrupt enabled 0 = START-OF-FRAME token interrupt disabled STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt enabled 0 = STALL interrupt disabled IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle detect interrupt enabled 0 = Idle detect interrupt disabled TRNIE: Transaction Complete Interrupt Enable bit 1 = Transaction interrupt enabled 0 = Transaction interrupt disabled ACTVIE: Bus Activity Detect Interrupt Enable bit 1 = Bus activity detect interrupt enabled 0 = Bus activity detect interrupt disabled UERRIE: USB Error Interrupt Enable bit 1 = USB error interrupt enabled 0 = USB error interrupt disabled URSTIE: USB Reset Interrupt Enable bit 1 = USB Reset interrupt enabled 0 = USB Reset interrupt disabled
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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14.5.3 USB ERROR INTERRUPT STATUS REGISTER (UEIR)
The USB Error Interrupt Status register (Register 14-9) contains the flag bits for each of the error sources within the USB peripheral. Each of these sources is controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic. Each error bit is set as soon as the error condition is detected. Thus, the interrupt will typically not correspond with the end of a token being processed. Once an interrupt bit has been set by the SIE, it must be cleared by software by writing a `0'.
REGISTER 14-9:
R/C-0 BTSEF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
UEIR: USB ERROR INTERRUPT STATUS REGISTER
U-0 -- U-0 -- R/C-0 BTOEF R/C-0 DFN8EF R/C-0 CRC16EF R/C-0 CRC5EF R/C-0 PIDEF bit 0
C = Clearable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
BTSEF: Bit Stuff Error Flag bit 1 = A bit stuff error has been detected 0 = No bit stuff error Unimplemented: Read as `0' BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed) 0 = No bus turnaround time-out DFN8EF: Data Field Size Error Flag bit 1 = The data field was not an integral number of bytes 0 = The data field was an integral number of bytes CRC16EF: CRC16 Failure Flag bit 1 = The CRC16 failed 0 = The CRC16 passed CRC5EF: CRC5 Host Error Flag bit 1 = The token packet was rejected due to a CRC5 error 0 = The token packet was accepted PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed
bit 6-5 bit 4
bit 3
bit 2
bit 1
bit 0
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14.5.4 USB ERROR INTERRUPT ENABLE REGISTER (UEIE)
The USB Error Interrupt Enable register (Register 14-10) contains the enable bits for each of the USB error interrupt sources. Setting any of these bits will enable the respective error interrupt source in the UEIR register to propagate into the UERR bit at the top level of the interrupt logic. As with the UIE register, the enable bits only affect the propagation of an interrupt condition to the microcontroller's interrupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt.
REGISTER 14-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER
R/W-0 BTSEE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 BTOEE R/W-0 DFN8EE R/W-0 CRC16EE R/W-0 CRC5EE R/W-0 PIDEE bit 0
BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Bit stuff error interrupt enabled 0 = Bit stuff error interrupt disabled Unimplemented: Read as `0' BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Bus turnaround time-out error interrupt enabled 0 = Bus turnaround time-out error interrupt disabled DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Data field size error interrupt enabled 0 = Data field size error interrupt disabled CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16 failure interrupt enabled 0 = CRC16 failure interrupt disabled CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = CRC5 host error interrupt enabled 0 = CRC5 host error interrupt disabled PIDEE: PID Check Failure Interrupt Enable bit 1 = PID check failure interrupt enabled 0 = PID check failure interrupt disabled
bit 6-5 bit 4
bit 3
bit 2
bit 1
bit 0
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14.6 USB Power Modes
14.6.3
Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are Bus Power Only, Self-Power Only and Dual Power with Self-Power Dominance. The most common cases are presented here.
DUAL POWER WITH SELF-POWER DOMINANCE
14.6.1
BUS POWER ONLY
Some applications may require a dual power option. This allows the application to use internal power primarily, but switch to power from the USB when no internal power is available. Figure 14-12 shows a simple Dual Power with Self-Power Dominance example, which automatically switches between Self-Power Only and USB Bus Power Only modes.
In Bus Power Only mode, all power for the application is drawn from the USB (Figure 14-10). This is effectively the simplest power method for the device.
FIGURE 14-12:
DUAL POWER EXAMPLE
I/O pin
100 k Attach Sense
FIGURE 14-10:
BUS POWER ONLY
VBUS ~5V
VDD
VBUS ~5V
VDD
100 k VSELF ~5V
VUSB VSS
VUSB VSS
Note:
14.6.2
SELF-POWER ONLY
In Self-Power Only mode, the USB application provides its own power, with very little power being pulled from the USB. Figure 14-11 shows an example. Note that an attach indication is added to indicate when the USB has been connected.
Users should keep in mind the limits for devices drawing power from the USB. According to USB Specification 2.0, this cannot exceed 100 mA per low-power device or 500 mA per high-power device.
14.7
Oscillator
FIGURE 14-11:
VBUS ~5V VSELF ~5V 100 k
SELF-POWER ONLY
I/O pin 100 k VDD
Attach Sense
The USB module has specific clock requirements. For full-speed operation, the clock source must be 48 MHz. Even so, the microcontroller core and other peripherals are not required to run at that clock speed or even from the same clock source. Available clocking options are described in detail in Section 2.3 "Oscillator Settings for USB".
VUSB VSS
14.8
USB Firmware and Drivers
Microchip provides a number of application-specific resources, such as USB firmware and driver support. Refer to www.microchip.com for the latest firmware and driver support.
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TABLE 14-6:
Name INTCON IPR2 PIR2 PIE2 UCON UCFG USTAT UADDR UFRML UFRMH UIR UIE UEIR UEIE UEP0 UEP1 UEP2 UEP3 UEP4 UEP5 UEP6 UEP7 UEP8 UEP9 UEP10 UEP11 UEP12 UEP13 UEP14 UEP15 Legend: Note 1:
REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)
Bit 7 Bit 6 PEIE/GIEL -- -- -- PPBRST UOEMON ENDP3 ADDR6 FRM6 -- SOFIF SOFIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 TMR0IE USBIP USBIF USBIE SE0 -- ENDP2 ADDR5 FRM5 -- STALLIF STALLIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 INT0IE -- -- -- PKTDIS UPUEN ENDP1 ADDR4 FRM4 -- IDLEIF IDLEIE BTOEF BTOEE EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK Bit 3 RBIE -- -- -- USBEN UTRDIS ENDP0 ADDR3 FRM3 -- TRNIF TRNIE DFN8EF DFN8EE Bit 2 TMR0IF HLVDIP HLVDIF HLVDIE RESUME FSEN DIR ADDR2 FRM2 FRM10 ACTVIF ACTVIE CRC16EF CRC16EE Bit 1 INT0IF -- -- -- SUSPND PPB1 PPBI ADDR1 FRM1 FRM9 UERRIF UERRIE CRC5EF CRC5EE EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN EPINEN Bit 0 RBIF -- -- -- -- PPB0 -- ADDR0 FRM0 FRM8 URSTIF URSTIE PIDEF PIDEE EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL Details on page 49 51 51 51 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 51 51 51 51 51 51 51
GIE/GIEH OSCFIP OSCFIF OSCFIE -- UTEYE -- -- FRM7 -- -- -- BTSEF BTSEE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN EPCONDIS EPOUTEN
-- = unimplemented, read as `0'. Shaded cells are not used by the USB module. This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 14-5.
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14.9 Overview of USB
14.9.3 TRANSFERS
This section presents some of the basic USB concepts and useful information necessary to design a USB device. Although much information is provided in this section, there is a plethora of information provided within the USB specifications and class specifications. Thus, the reader is encouraged to refer to the USB specifications for more information (www.usb.org). If you are very familiar with the details of USB, then this section serves as a basic, high-level refresher of USB. There are four transfer types defined in the USB specification. * Isochronous: This type provides a transfer method for large amounts of data (up to 1023 bytes) with timely delivery ensured; however, the data integrity is not ensured. This is good for streaming applications where small data loss is not critical, such as audio. * Bulk: This type of transfer method allows for large amounts of data to be transferred with ensured data integrity; however, the delivery timeliness is not ensured. * Interrupt: This type of transfer provides for ensured timely delivery for small blocks of data; plus data integrity is ensured. * Control: This type provides for device setup control. While full-speed devices support all transfer types, low-speed devices are limited to interrupt and control transfers only.
14.9.1
LAYERED FRAMEWORK
USB device functionality is structured into a layered framework graphically shown in Figure 14-13. Each level is associated with a functional level within the device. The highest layer, other than the device, is the configuration. A device may have multiple configurations. For example, a particular device may have multiple power requirements based on Self-Power Only or Bus Power Only modes. For each configuration, there may be multiple interfaces. Each interface could support a particular mode of that configuration. Below the interface is the endpoint(s). Data is directly moved at this level. There can be as many as 16 bidirectional endpoints. Endpoint 0 is always a control endpoint and by default, when the device is on the bus, Endpoint 0 must be available to configure the device.
14.9.4
POWER
Power is available from the Universal Serial Bus. The USB specification defines the bus power requirements. Devices may either be self-powered or bus powered. Self-powered devices draw power from an external source, while bus powered devices use power supplied from the bus.
14.9.2
FRAMES
Information communicated on the bus is grouped into 1 ms time slots, referred to as frames. Each frame can contain many transactions to various devices and endpoints. Figure 14-9 shows an example of a transaction within a frame.
FIGURE 14-13:
USB LAYERS
Device
To other Configurations (if any)
Configuration To other Interfaces (if any)
Interface
Interface
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
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The USB specification limits the power taken from the bus. Each device is ensured 100 mA at approximately 5V (one-unit load). Additional power may be requested, up to a maximum of 500 mA. Note that power above a oneunit load is a request and the host or hub is not obligated to provide the extra current. Thus, a device capable of consuming more than a one-unit load must be able to maintain a low-power configuration of a one-unit load or less, if necessary. The USB specification also defines a Suspend mode. In this situation, current must be limited to 500 A, averaged over 1 second. A device must enter a Suspend state after 3 ms of inactivity (i.e., no SOF tokens for 3 ms). A device entering Suspend mode must drop current consumption within 10 ms after Suspend. Likewise, when signaling a wake-up, the device must signal a wake-up within 10 ms of drawing current above the Suspend limit.
14.9.6.2
Configuration Descriptor
The configuration descriptor provides information on the power requirements of the device and how many different interfaces are supported when in this configuration. There may be more than one configuration for a device (i.e., low-power and high-power configurations).
14.9.6.3
Interface Descriptor
The interface descriptor details the number of endpoints used in this interface, as well as the class of the interface. There may be more than one interface for a configuration.
14.9.6.4
Endpoint Descriptor
14.9.5
ENUMERATION
When the device is initially attached to the bus, the host enters an enumeration process in an attempt to identify the device. Essentially, the host interrogates the device, gathering information such as power consumption, data rates and sizes, protocol and other descriptive information; descriptors contain this information. A typical enumeration process would be as follows: 1. USB Reset: Reset the device. Thus, the device is not configured and does not have an address (address 0). Get Device Descriptor: The host requests a small portion of the device descriptor. USB Reset: Reset the device again. Set Address: The host assigns an address to the device. Get Device Descriptor: The host retrieves the device descriptor, gathering info such as manufacturer, type of device, maximum control packet size. Get configuration descriptors. Get any other descriptors. Set a configuration.
The endpoint descriptor identifies the transfer type (Section 14.9.3 "Transfers") and direction, as well as some other specifics for the endpoint. There may be many endpoints in a device and endpoints may be shared in different configurations.
14.9.6.5
String Descriptor
Many of the previous descriptors reference one or more string descriptors. String descriptors provide human readable information about the layer (Section 14.9.1 "Layered Framework") they describe. Often these strings show up in the host to help the user identify the device. String descriptors are generally optional to save memory and are encoded in a unicode format.
2. 3. 4. 5.
14.9.7
BUS SPEED
Each USB device must indicate its bus presence and speed to the host. This is accomplished through a 1.5 k resistor which is connected to the bus at the time of the attachment event. Depending on the speed of the device, the resistor either pulls up the D+ or D- line to 3.3V. For a lowspeed device, the pull-up resistor is connected to the D- line. For a full-speed device, the pull-up resistor is connected to the D+ line.
6. 7. 8.
14.9.8
The exact enumeration process depends on the host.
CLASS SPECIFICATIONS AND DRIVERS
14.9.6
DESCRIPTORS
There are eight different standard descriptor types of which five are most important for this device.
14.9.6.1
Device Descriptor
The device descriptor provides general information, such as manufacturer, product number, serial number, the class of the device and the number of configurations. There is only one device descriptor.
USB specifications include class specifications which operating system vendors optionally support. Examples of classes include Audio, Mass Storage, Communications and Human Interface (HID). In most cases, a driver is required at the host side to `talk' to the USB device. In custom applications, a driver may need to be developed. Fortunately, drivers are available for most common host systems for the most common classes of devices. Thus, these drivers can be reused.
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NOTES:
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15.0 ENHANCED UNIVERSAL SYNCHRONOUS RECEIVER TRANSMITTER (EUSART)
The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX/ DT as an EUSART: * bit SPEN (RCSTA<7>) must be set (= 1) * bit TRISC<7> must be set (= 1) * bit TRISC<6> must be cleared (= 0) for Asynchronous and Synchronous Master modes or set (= 1) for Synchronous Slave mode Note: The EUSART control will automatically reconfigure the pin from input to output as needed.
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs and so on. The Enhanced Universal Synchronous Receiver Transmitter (EUSART) module implements additional features, including Automatic Baud Rate Detection (ABD) and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These features make it ideally suited for use in Local Interconnect Network bus (LIN bus) systems. The EUSART can be configured in the following modes: * Asynchronous (full-duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission * Synchronous - Master (half-duplex) with selectable clock polarity * Synchronous - Slave (half-duplex) with selectable clock polarity
The operation of the Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCON) These are detailed on the following pages in Register 15-1, Register 15-2 and Register 15-3, respectively.
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REGISTER 15-1:
R/W-0 CSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 TX9 R/W-0 TXEN(1) R/W-0 SYNC R/W-0 SENDB R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care. BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous Slave mode.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 15-2:
R/W-0 SPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don't care. FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 15-3:
R/W-0 ABDOVF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
BAUDCON: BAUD RATE CONTROL REGISTER
R-1 RCIDL U-0 -- R/W-0 SCKP R/W-0 BRG16 U-0 -- R/W-0 WUE R/W-0 ABDEN bit 0
ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active Unimplemented: Read as `0' SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator - SPBRG only (Compatible mode), SPBRGH value ignored Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode.
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
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15.1 Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also control the baud rate. In Synchronous mode, BRGH is ignored. Table 15-1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 15-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 15-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 15-2. It may be advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
15.1.1
OPERATION IN POWER-MANAGED MODES
The device clock is used to generate the desired baud rate. When one of the power-managed modes is entered, the new clock source may be operating at a different frequency. This may require an adjustment to the value in the SPBRG register pair.
15.1.2
SAMPLING
The data on the RX pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
TABLE 15-1:
SYNC
BAUD RATE FORMULAS
BRG16 BRGH BRG/EUSART Mode Baud Rate Formula FOSC/[64 (n + 1)] FOSC/[16 (n + 1)]
Configuration Bits
0 0 0 8-bit/Asynchronous 0 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous Legend: x = Don't care, n = value of SPBRGH:SPBRG register pair
FOSC/[4 (n + 1)]
EXAMPLE 15-1:
CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16%
TABLE 15-2:
Name
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX9D RX9D ABDEN Reset Values on page 51 51 51 50 50
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR BAUDCON ABDOVF RCIDL -- SCKP BRG16 -- WUE SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the BRG.
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TABLE 15-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz Actual Rate (K) -- 1.221 2.404 9.766 19.531 62.500 104.167 % Error -- 1.73 0.16 1.73 1.73 8.51 -9.58 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) -- 1.202 2.404 9.766 19.531 52.083 78.125 % Error -- 0.16 0.16 1.73 1.73 -9.58 -32.18 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) -- 1201 2403 9615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- -- 255 64 31 10 4
-- 255 129 31 15 4 2
-- 129 64 15 7 2 1
-- 103 51 12 -- -- --
SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 8.929 20.833 62.500 62.500 % Error 0.16 0.16 0.16 -6.99 8.51 8.51 -45.75 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 300 1201 2403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 300 1201 -- -- -- -- -- % Error -0.16 -0.16 -- -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
207 51 25 6 2 0 0
103 25 12 -- -- -- --
51 12 -- -- -- -- --
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) -- -- -- 9.766 19.231 58.140 113.636 % Error -- -- -- 1.73 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 20.000 MHz Actual Rate (K) -- -- -- 9.615 19.231 56.818 113.636 % Error -- -- -- 0.16 0.16 -1.36 -1.36 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) -- -- 2403 9615 19230 55555 -- % Error -- -- -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- -- -- 255 129 42 21
-- -- -- 129 64 21 10
-- -- 255 64 31 10 4
-- -- 207 51 25 8 --
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) -- 1.202 2.404 9.615 19.231 62.500 125.000 % Error -- 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) -- 1201 2403 9615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 300 1201 2403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- 207 103 25 12 3 1
-- 103 51 12 -- -- --
207 51 25 -- -- -- --
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TABLE 15-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.399 9.615 19.231 56.818 113.636 % Error 0.02 -0.03 -0.03 0.16 0.16 -1.36 -1.36 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.531 56.818 125.000 % Error 0.02 -0.03 0.16 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) 300 1201 2403 9615 19230 55555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
8332 2082 1040 259 129 42 21
4165 1041 520 129 64 21 10
2082 520 259 64 31 10 4
1665 415 207 51 25 8 --
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 9.615 19.231 62.500 125.000 % Error 0.04 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 300 1201 2403 9615 -- -- -- % Error -0.16 -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 300 1201 2403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
832 207 103 25 12 3 1
415 103 51 12 -- -- --
207 51 25 -- -- -- --
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.606 19.193 57.803 114.943 % Error 0.00 0.00 0.02 0.06 -0.03 0.35 -0.22 SPBRG value
(decimal)
FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.596 19.231 57.471 116.279 % Error 0.00 0.02 0.02 -0.03 0.16 -0.22 0.94 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) 300 1200 2400 9615 19230 57142 117647 % Error -0.01 -0.04 -0.04 -0.16 -0.16 0.79 -2.12 SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
33332 8332 4165 1040 520 172 86
16665 4165 2082 520 259 86 42
8332 2082 1040 259 129 42 21
6665 1665 832 207 103 34 16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.231 58.824 111.111 % Error 0.01 0.04 0.16 0.16 0.16 2.12 -3.55 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 300 1201 2403 9615 19230 55555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 300 1201 2403 9615 19230 -- -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
3332 832 415 103 51 16 8
1665 415 207 51 25 8 --
832 207 103 25 12 -- --
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15.1.3 AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 15-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detection must receive a byte with the value 55h (ASCII "U", which is also the LIN bus Sync character) in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up, using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin, or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. If a rollover of the BRG occurs (an overflow from FFFFh to 0000h), the event is trapped by the ABDOVF status bit (BAUDCON<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software. ABD mode remains active after rollover events and the ABDEN bit remains set (Figure 15-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table 15-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature.
TABLE 15-4:
BRG16 0 0 1 1 Note: BRGH 0 1 0 1
BRG COUNTER CLOCK RATES
BRG Counter Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32
During the ABD sequence, SPBRG and SPBRGH are both used as a 16-bit counter, independent of the BRG16 setting.
15.1.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREG cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation.
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FIGURE 15-1:
BRG Value
AUTOMATIC BAUD RATE CALCULATION
XXXXh 0000h Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 001Ch Edge #5 Stop bit Start
RX pin
BRG Clock Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG SPBRGH XXXXh XXXXh 1Ch 00h Auto-Cleared
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 15-2:
BRG Clock ABDEN bit RX pin ABDOVF bit
BRG OVERFLOW SEQUENCE
Start
bit 0
FFFFh BRG Value XXXXh 0000h 0000h
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15.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses the standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is eight bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity is not supported by the hardware but can be implemented in software and stored as the ninth data bit. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-Bit Break Character Transmit Auto-Baud Rate Detection Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF will be set regardless of the state of TXIE; it cannot be cleared in software. TXIF is also not cleared immediately upon loading TXREG but becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. To set up an Asynchronous Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
2. 3. 4. 5. 6. 7. 8.
15.2.1
EUSART ASYNCHRONOUS TRANSMITTER
The EUSART transmitter block diagram is shown in Figure 15-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available).
FIGURE 15-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXREG Register 8 MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPEN *** TSR Register LSb 0 Pin Buffer and Control TX pin
TXIE
BRG16
SPBRGH
SPBRG
TX9 TX9D
Baud Rate Generator
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FIGURE 15-4:
Write to TXREG BRG Output (Shift Clock) TX (pin) TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1
ASYNCHRONOUS TRANSMISSION
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
1 TCY
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 15-5:
Write to TXREG
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Word 1 Word 2
BRG Output (Shift Clock) TX (pin) TXIF bit (Interrupt Reg. Flag) 1 TCY 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Start bit bit 0 bit 1 Word 1 bit 7/8 Start bit Word 2 bit 0
Stop bit
This timing diagram shows two consecutive transmissions.
TABLE 15-5:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 49 51 51 51 51 50 51 51 50 50
GIE/GIEH PEIE/GIEL -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission.
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15.2.2 EUSART ASYNCHRONOUS RECEIVER 15.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT
The receiver block diagram is shown in Figure 15-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. 1.
FIGURE 15-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN x64 Baud Rate CLK OERR FERR
BRG16
SPBRGH
SPBRG
Baud Rate Generator
/ 64 or / 16 or /4
MSb Stop (8) 7
RSR Register *** 1 0
LSb Start
RX9 Pin Buffer and Control RX Data Recovery RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF RCIE Data Bus
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FIGURE 15-7:
RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. Word 1 RCREG
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 2 RCREG
TABLE 15-6:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 49 51 51 51 51 50 51 51 50 50 --
GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL RCIF RCIE RCIP SREN TXEN
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception.
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15.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER
During Sleep mode, all clocks to the EUSART are suspended. Therefore, the Baud Rate Generator is inactive and proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>). Once set, the typical receive sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 15-8) and asynchronously if the device is in Sleep mode (Figure 15-9). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared once a low-to-high transition is observed on the RX line following the wakeup event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. Character and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., XT or HS mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART.
15.2.4.2
Special Considerations Using the WUE Bit
The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/ DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode.
15.2.4.1
Special Considerations Using Auto-Wake-up
Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false End-of-
FIGURE 15-8:
OSC1
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit set by user WUE bit(1) RX/DT Line RCIF Cleared due to user read of RCREG
Auto-Cleared
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 15-9:
OSC1
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit set by user WUE bit(2) RX/DT Line RCIF Sleep Command Executed Note 1: 2: Sleep Ends Note 1 Cleared due to user read of RCREG
Auto-Cleared
If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.
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15.2.5 BREAK CHARACTER SEQUENCE
3. 4. 5. The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift Register is loaded with data. Note that the value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). Note that the data value written to the TXREG for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 15-10 for the timing of the Break character sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode.
When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG.
15.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and eight data bits for typical data). The second method uses the auto-wake-up feature described in Section 15.2.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed.
15.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to set up the Break character.
FIGURE 15-10:
Write to TXREG BRG Output (Shift Clock) TX (pin)
SEND BREAK CHARACTER SEQUENCE
Dummy Write
Start bit
bit 0
bit 1 Break
bit 11
Stop bit
TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here SENDB (Transmit Shift Reg. Empty Flag) Auto-Cleared
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15.3 EUSART Synchronous Master Mode
Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG register is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF is set regardless of the state of enable bit TXIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user must poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. To set up a Synchronous Master Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order to configure the TX and RX pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCON<4>). Setting SCKP sets the Idle state on CK as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module.
15.3.1
EUSART SYNCHRONOUS MASTER TRANSMISSION
2. 3. 4. 5. 6. 7. 8.
The EUSART transmitter block diagram is shown in Figure 15-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available).
FIGURE 15-11:
SYNCHRONOUS TRANSMISSION
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 RC6/TX/CK pin (SCKP = 0) RC6/TX/CK pin (SCKP = 1) Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1'
Word 2
Write Word 1
Write Word 2
`1'
Sync Master mode (SPBRG = 0), continuous transmission of two 8-bit words.
DS39760A-page 168
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FIGURE 15-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 2 bit 6 bit 7 RC7/RX/DT pin
RC6/TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 15-7:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 49 51 51 51 51 50 51 51 50 50 --
GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL RCIF RCIE RCIP SREN TXEN
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission.
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15.3.2 EUSART SYNCHRONOUS MASTER RECEPTION
Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RX pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 3. 4. 5. 6.
2.
FIGURE 15-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin (SCKP = 0) RC6/TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' RCIF bit (Interrupt) Read RXREG Note:
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
`0'
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 15-8:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 Bit 6 PEIE/GIEL ADIF ADIE ADIP RX9 TX9 RCIDL Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 49 51 51 51 51 50 51 51 51 50
GIE/GIEH -- -- -- SPEN CSRC
EUSART Receive Register
BAUDCON ABDOVF
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception.
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15.4 EUSART Synchronous Slave Mode
To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode.
2. 3. 4. 5. 6. 7. 8.
15.4.1
EUSART SYNCHRONOUS SLAVE TRANSMIT
The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep mode. If two words are written to the TXREG register and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector.
e)
TABLE 15-9:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 49 51 51 51 51 50 51 51 50 50
GIE/GIEH PEIE/GIEL -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission.
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15.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION
To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the chip from the lowpower mode. If the global interrupt is enabled, the program will branch to the interrupt vector.
2. 3. 4. 5.
6.
7. 8. 9.
TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA BAUDCON SPBRGH SPBRG Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 49 51 51 51 51 50 51 51 50 50 --
GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL RCIF RCIE RCIP SREN TXEN
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception.
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16.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The ADCON0 register, shown in Register 16-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 16-2, configures the functions of the port pins. The ADCON2 register, shown in Register 16-3, configures the A/D clock source, programmed acquisition time and justification.
The Analog-to-Digital (A/D) converter module has 10 inputs for the 28-pin devices and 13 for the 40/44-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. The module has five registers: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2)
REGISTER 16-1:
U0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-2
ADCON0: A/D CONTROL REGISTER 0
U-0 -- R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled These channels are not implemented on 28-pin devices. Performing a conversion on unimplemented channels will return a floating input measurement.
bit 1
bit 0
Note 1: 2:
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REGISTER 16-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON1: A/D CONTROL REGISTER 1
U-0 -- R/W-0 VCFG0 R/W-0 VCFG0 R/W-0(1) PCFG3 R/W(1) PCFG2 R/W(1) PCFG1 R/W(1) PCFG0 bit 0
Unimplemented: Read as `0' VCFG0: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = VSS VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = VDD PCFG3:PCFG0: A/D Port Configuration Control bits: AN7(2) AN6(2) AN9 AN8 AN4 AN3 AN2 AN1 A A A A A A A A A A A A A A D D AN0 A A A A A A A A A A A A A A A D PCFG3: PCFG0 0000(1) 0001 0010 0011 0100 0101 0110 0111(1) 1000 1001 1010 1011 1100 1101 1110 1111 AN5(2) A A A A A A A A A A D D D D D D AN12 AN10 A A A A A D D D D D D D D D D D AN11 A A A A D D D D D D D D D D D D
bit 4
bit 3-0
A A A D D D D D D D D D D D D D
A A A A A A D D D D D D D D D D
A A A A A A A D D D D D D D D D
A A A A A A A A D D D D D D D D
A A A A A A A A A D D D D D D D
A A A A A A A A A A A D D D D D
A A A A A A A A A A A A D D D D
A A A A A A A A A A A A A D D D
A = Analog input
D = Digital I/O
Note 1: 2:
The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111. AN5 through AN7 are available only on 40/44-pin devices.
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REGISTER 16-3:
R/W-0 ADFM bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON2: A/D CONTROL REGISTER 2
U-0 -- R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0
ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified Unimplemented: Read as `0' ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
bit 6 bit 5-3
bit 2-0
Note 1:
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The analog reference voltage is software selectable to either the device's positive and negative supply voltage (VDD and VSS) or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF- pins. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 16-1.
FIGURE 16-1:
A/D BLOCK DIAGRAM
CHS3:CHS0 1100 1011 1010 1001 1000 0111 0110 0101 0100 VAIN 10-Bit Converter A/D (Input Voltage) 0011 0010 VCFG1:VCFG0 VDD(2) VREF+ VREFX0 X1
AN12 AN11 AN10 AN9 AN8 AN7(1) AN6(1) AN5(1) AN4 AN3 AN2 AN1 AN0
0001 0000
Reference Voltage
1X 0X VSS(2)
Note 1: 2:
Channels AN5 through AN7 are not available on 28-pin devices. I/O pins have diode protection to VDD and VSS.
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The value in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 16.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. The following steps should be followed to perform an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0 register)
Digital Code Output
5.
Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 3 TAD is required before the next acquisition starts.
6. 7.
FIGURE 16-2:
3FFh 3FEh
A/D TRANSFER FUNCTION
003h 002h 001h 000h
2.
1022.5 LSB
3. 4.
Analog Input Voltage
FIGURE 16-3:
ANALOG INPUT MODEL
VDD VT = 0.6V Rs ANx RIC 1k Sampling Switch SS RSS
VAIN
CPIN 5 pF
VT = 0.6V
ILEAKAGE 100 nA
CHOLD = 25 pF
VSS
Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch SS = Sample/hold Capacitance (from DAC) CHOLD RSS = Sampling Switch Resistance
VDD
6V 5V 4V 3V 2V
1
2
3
4
Sampling Switch (k)
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1023.5 LSB
0.5 LSB
1.5 LSB
2.5 LSB
3 LSB
1022 LSB
1023 LSB
1 LSB
2 LSB
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16.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 16-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. To calculate the minimum acquisition time, Equation 16-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 16-3 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature = = = = 25 pF 2.5 k 1/2 LSb 5V RSS = 2 k 85C (system max.)
EQUATION 16-1:
TACQ = =
ACQUISITION TIME
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF
EQUATION 16-2:
VHOLD or TC = =
A/D MINIMUM CHARGING TIME
(VREF - (VREF/2048)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) -(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 16-3:
TACQ TAMP TCOFF = = = 0.2 s
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TAMP + TC + TCOFF (Temp - 25C)(0.02 s/C) (85C - 25C)(0.02 s/C) 1.2 s -(CHOLD)(RIC + RSS + RS) ln(1/2047) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 s 0.2 s + 1 s + 1.2 s 2.4 s
Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC =
TACQ
=
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16.2 Selecting and Configuring Acquisition Time 16.3 Selecting the A/D Conversion Clock
The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. Acquisition time may be set with the ACQT2:ACQT0 bits (ADCON2<5:3>) which provide a range of 2 to 20 TAD. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. Manual acquisition is selected when ACQT2:ACQT0 = 000. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This option is also the default Reset state of the ACQT2:ACQT0 bits and is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun.
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD (see parameter 130 in Table 21-18 for more information). Table 16-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 16-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Maximum Device Frequency PIC18FXXXX 2.86 MHz 5.71 MHz 11.43 MHz 22.86 MHz 40.0 MHz 40.0 MHz 1.00 MHz(1) PIC18LFXXXX(4) 1.43 kHz 2.86 MHz 5.72 MHz 11.43 MHz 22.86 MHz 22.86 MHz 1.00 MHz(2)
Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC(3) Note 1: 2: 3: 4:
ADCS2:ADCS0 000 100 001 101 010 110 x11
The RC source has a typical TAD time of 1.2 s. The RC source has a typical TAD time of 2.5 s. For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. Low-power devices only.
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16.4 Operation in Power-Managed Modes 16.5 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert as analog inputs. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. 3: The PBADEN bit in Configuration Register 3H configures PORTB pins to reset as analog or digital pins by controlling how the PCFG0 bits in ADCON1 are reset.
The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started. Once started, the device should continue to be clocked by the same clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in the Sleep mode requires the A/D FRC clock to be selected. If bits ACQT2:ACQT0 are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion.
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16.6 A/D Conversions
Figure 16-4 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 16-5 shows the operation of the A/D converter after the GO/DONE bit has been set, the ACQT2:ACQT0 bits are set to `010' and selecting a 4 TAD acquisition time before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
16.7
Discharge
The discharge phase is used to initialize the value of the capacitor array. The array is discharged before every sample. This feature helps to optimize the unitygain amplifier as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measurement values.
FIGURE 16-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD1 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. Discharge
FIGURE 16-5:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TACQ Cycles 1 2 3 4 1 2 b9 Automatic Acquisition Time 3 b8 4 b7
TAD Cycles 5 b6 6 b5 7 b4 8 b3 9 b2 10 b1 11 b0 Discharge TAD1
Conversion starts (Holding capacitor is disconnected)
Set GO/DONE bit (Holding capacitor continues acquiring input)
On the following cycle: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.
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16.8 Use of the CCP1 Trigger
An A/D conversion can be started by the Special Event Trigger of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the Special Event Trigger sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D module but will still reset the Timer1 counter.
TABLE 16-2:
Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 PORTA TRISA PORTB TRISB LATB PORTE TRISE(4) LATE
(4)
REGISTERS ASSOCIATED WITH A/D OPERATION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP USBIF USBIE USBIP Bit 4 INT0IE TXIF TXIE TXIP -- -- -- Bit 3 RBIE -- -- -- -- -- -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP HLVDIF HLVDIE HLVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP -- -- -- Bit 0 RBIF TMR1IF TMR1IE TMR1IP -- -- -- Reset Values on page 49 51 51 51 51 51 51 50 50 CHS2 VCFG0 ACQT1 RA4 TRISA4 RB4 TRISB4 LATB4 -- -- -- CHS1 PCFG3 ACQT0 RA3 TRISA3 RB3 TRISB3 LATB3 RE3(1,3) -- -- CHS0 PCFG2 ADCS2 RA2 TRISA2 RB2 TRISB2 LATB2 RE2(4) LATE2(4) GO/DONE PCFG1 ADCS1 RA1 TRISA1 RB1 TRISB1 LATB1 RE1(4) LATE1(4) ADON PCFG0 ADCS0 RA0 TRISA0 RB0 TRISB0 LATB0 RE0(4) LATE0(4) 50 50 50 51 51 51 51 51 51 51 51
GIE/GIEH PEIE/GIEL -- -- -- OSCFIF OSCFIE OSCFIP ADIF ADIE ADIP -- -- --
A/D Result Register High Byte A/D Result Register Low Byte -- -- ADFM -- -- RB7 TRISB7 LATB7 -- -- -- -- -- -- RA6(2) TRISA6(2) RB6 TRISB6 LATB6 -- -- -- CHS3 VCFG1 ACQT2 RA5 TRISA5 RB5 TRISB5 LATB5 -- -- --
TRISE2(4) TRISE1(4) TRISE0(4)
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'. 3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is `0'. 4: These registers and/or bits are not implemented on 28-pin devices.
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17.0 HIGH/LOW-VOLTAGE DETECT (HLVD)
The High/Low-Voltage Detect Control register (Register 17-1) completely controls the operation of the HLVD module. This allows the circuitry to be "turned off" by the user under software control which minimizes the current consumption for the device. The block diagram for the HLVD module is shown in Figure 17-1.
PIC18F2450/4450 devices have a High/Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt.
REGISTER 17-1:
R/W-0 VDIRMAG bit 7 Legend: R = Readable bit -n = Value at POR bit 7
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
U-0 -- R-0 IRVST R/W-0 HLVDEN R/W-0 HLVDL3(1) R/W-1 HLVDL2(1) R/W-0 HLVDL1(1) R/W-1 HLVDL0(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0) 0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0) Unimplemented: Read as `0' IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage trip point 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage trip point and the LVD interrupt should not be enabled HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled HLVDL3:HLVDL0: Voltage Detection Limit bits(1) 1111 = Reserved 1110 = Maximum setting . . . 0000 = Minimum setting See Table 21-4 in Section 21.0 "Electrical Characteristics" for specifications.
bit 6 bit 5
bit 4
bit 3-0
Note 1:
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The module is enabled by setting the HLVDEN bit. Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. The VDIRMAG bit determines the overall operation of the module. When VDIRMAG is cleared, the module monitors for drops in VDD below a predetermined set point. When the bit is set, the module monitors for rises in VDD above the set point. event, depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. The trip point voltage is software programmable to any one of 16 values. The trip point is selected by programming the HLVDL3:HLVDL0 bits (HLVDCON<3:0>). The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits, HLVDL3:HLVDL0, are set to `1111'. In this state, the comparator input is multiplexed from the external input pin, HLVDIN. This gives users flexibility because it allows them to configure the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range.
17.1
Operation
When the HLVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The "trip point" voltage is the voltage level at which the device detects a high or low-voltage
FIGURE 17-1:
HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)
Externally Generated Trip Point VDD VDD HLVDL3:HLVDL0 HLVDCON Register VDIRMAG
HLVDIN
HLVDEN
16-to-1 MUX
Set HLVDIF
HLVDEN
BOREN
Internal Voltage Reference 1.2V Typical
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17.2 HLVD Setup
The following steps are needed to set up the HLVD module: 1. 2. 3. 4. 5. Disable the module by clearing the HLVDEN bit (HLVDCON<4>). Write the value to the HLVDL3:HLVDL0 bits that selects the desired HLVD trip point. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD Interrupt Flag, HLVDIF (PIR2<2>), which may have been set from a previous interrupt. Enable the HLVD interrupt, if interrupts are desired, by setting the HLVDIE and GIE/GIEH bits (PIE2<2> and INTCON<7>). An interrupt will not be generated until the IRVST bit is set. Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the HLVD module may be disabled.
17.4
HLVD Start-up Time
6.
The internal reference voltage of the HLVD module, specified in electrical specification parameter D420 (see Table 21-4 in Section 21.0 "Electrical Characteristics"), may be used by other internal circuitry, such as the Programmable Brown-out Reset. If the HLVD or other circuits using the voltage reference are disabled to lower the device's current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification parameter 36 (Table 21-10). The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval. Refer to Figure 17-2 or Figure 17-3.
17.3
Current Consumption
When the module is enabled, the HLVD comparator and voltage divider are enabled and will consume static current. The total current consumption, when enabled, is specified in electrical specification parameter D022 (Section 268 "DC Characteristics").
FIGURE 17-2:
CASE 1: VDD
LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
HLVDIF may not be set
VHLVD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable CASE 2: VDD VHLVD HLVDIF Enable HLVD IRVST Internal Reference is stable TIRVST HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists HLVDIF cleared in software
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FIGURE 17-3:
CASE 1:
HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
HLVDIF may not be set VHLVD VDD
HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD
HLVDIF Enable HLVD IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists TIRVST
17.5
Applications
FIGURE 17-4:
For general battery applications, Figure 17-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an ISR, which would allow the application to perform "housekeeping tasks" and perform a controlled shutdown before the device voltage exits the valid operating range at TB. The HLVD, thus, would give the application a time window, represented by the difference between TA and TB, to safely exit.
Voltage
In many applications, the ability to detect a drop below or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin).
TYPICAL HIGH/LOW-VOLTAGE DETECT APPLICATION
VA VB
Time
TA
TB
Legend: VA = HLVD trip point VB = Minimum valid device operating voltage
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17.6 Operation During Sleep 17.7 Effects of a Reset
When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
TABLE 17-1:
Name HLVDCON INTCON PIR2 PIE2 IPR2
REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Bit 7 Bit 6 -- -- -- -- Bit 5 IRVST TMR0IE USBIF USBIE USBIP Bit 4 HLVDEN INT0IE -- -- -- Bit 3 HLVDL3 RBIE -- -- -- Bit 2 HLVDL2 TMR0IF HLVDIF HLVDIE HLVDIP Bit 1 HLVDL1 INT0IF -- -- -- Bit 0 HLVDL0 RBIF -- -- -- Reset Values on page 50 49 51 51 51
VDIRMAG OSCFIF OSCFIE OSCFIP
GIE/GIEH PEIE/GIEL
Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the HLVD module.
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18.0 SPECIAL FEATURES OF THE CPU
In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2450/4450 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits.
PIC18F2450/4450 devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * ID Locations * In-Circuit Serial Programming The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 2.0 "Oscillator Configurations". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet.
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18.1 Configuration Bits
The Configuration bits can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. Programming the Configuration registers is done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a self-timed write to the Configuration register. In normal operation mode, a TBLWT instruction, with the TBLPTR pointing to the Configuration register, sets up the address and the data for the Configuration register write. Setting the WR bit starts a long write to the Configuration register. The Configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. For additional details on Flash programming, refer to Section 6.5 "Writing to Flash Program Memory".
TABLE 18-1:
File Name 300000h 300001h 300002h 300003h 300005h 300006h 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh 3FFFFFh Legend: Note 1: 2:
CONFIGURATION BITS AND DEVICE IDs
Bit 7 -- IESO -- -- MCLRE DEBUG -- -- -- -- -- -- DEV2 DEV10 Bit 6 -- FCMEN -- -- -- XINST -- CPB -- WRTB -- EBTRB DEV1 DEV9 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 PLLDIV1 FOSC1 Bit 0 PLLDIV0 FOSC0 WDTEN -- STVREN CP0 -- WRT0 -- EBTR0 -- REV0 DEV3 Default/ Unprogrammed Value --00 0000 00-- 0101 --01 1111 ---1 1111 1--- -01100- 01-1 ---- --11 -1-- ------- --11 -11- ------- --11 -1-- ---xxxx xxxx(1) 0001 0010(1)
CONFIG1L CONFIG1H CONFIG2L CONFIG2H CONFIG3H CONFIG4L CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H DEVID2
USBDIV CPUDIV1 CPUDIV0 PLLDIV2 -- VREGEN -- -- ICPRT(2) -- -- -- WRTC -- -- DEV0 DEV8 -- BORV1 -- -- -- -- -- -- -- -- REV4 DEV7 FOSC3 BORV0 -- BBSIZ -- -- -- -- -- -- REV3 DEV6 FOSC2 BOREN1
BOREN0 PWRTEN
WDTPS3 WDTPS2 WDTPS1 WDTPS0 LPT1OSC PBADEN LVP -- -- -- -- -- -- REV2 DEV5 -- CP1 -- WRT1 -- EBTR1 -- REV1 DEV4
3FFFFEh DEVID1
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as `0'. See Register 18-13 and Register 18-14 for device ID values. DEVID registers are read-only and cannot be programmed by the user. Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.
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REGISTER 18-1:
U-0 -- bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-6 bit 5 Unimplemented: Read as `0' USBDIV: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) 1 = USB clock source comes from the 96 MHz PLL divided by 2 0 = USB clock source comes directly from the primary oscillator block with no postscale CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits For XT, HS, EC and ECIO Oscillator modes: 11 = Primary oscillator divided by 4 to derive system clock 10 = Primary oscillator divided by 3 to derive system clock 01 = Primary oscillator divided by 2 to derive system clock 00 = Primary oscillator used directly for system clock (no postscaler) For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes: 11 = 96 MHz PLL divided by 6 to derive system clock 10 = 96 MHz PLL divided by 4 to derive system clock 01 = 96 MHz PLL divided by 3 to derive system clock 00 = 96 MHz PLL divided by 2 to derive system clock PLLDIV2:PLLDIV0: PLL Prescaler Selection bits 111 = Divide by 12 (48 MHz oscillator input) 110 = Divide by 10 (40 MHz oscillator input) 101 = Divide by 6 (24 MHz oscillator input) 100 = Divide by 5 (20 MHz oscillator input) 011 = Divide by 4 (16 MHz oscillator input) 010 = Divide by 3 (12 MHz oscillator input) 001 = Divide by 2 (8 MHz oscillator input) 000 = No prescale (4 MHz oscillator input drives PLL directly)
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
U-0 -- R/P-0 USBDIV R/P-0 CPUDIV1 R/P-0 CPUDIV0 R/P-1 PLLDIV2 R/P-1 PLLDIV1 R/P-1 PLLDIV0 bit 0
bit 4-3
bit 2-0
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REGISTER 18-2:
R/P-0 IESO bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-0 U-0 -- U-0 -- R/P-0 FOSC3
(1)
R/P-1 FOSC2
(1)
R/P-1 FOSC1
(1)
R/P-1 FOSC0(1) bit 0
FCMEN
IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Unimplemented: Read as `0' FOSC3:FOSC0: Oscillator Selection bits(1) 111x = HS oscillator, PLL enabled (HSPLL) 110x = HS oscillator (HS) 1011 = Internal oscillator, HS oscillator used by USB (INTHS) 1010 = Internal oscillator, XT used by USB (INTXT) 1001 = Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO) 1000 = Internal oscillator, port function on RA6, EC used by USB (INTIO) 0111 = EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL) 0110 = EC oscillator, PLL enabled, port function on RA6 (ECPIO) 0101 = EC oscillator, CLKO function on RA6 (EC) 0100 = EC oscillator, port function on RA6 (ECIO) 001x = XT oscillator, PLL enabled (XTPLL) 000x = XT oscillator (XT) The microcontroller and USB module both use the selected oscillator as their clock source in XT, HS and EC modes. The USB module uses the indicated XT, HS or EC oscillator as its clock source whenever the microcontroller uses the internal oscillator.
bit 6
bit 5-4 bit 3-0
Note 1:
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REGISTER 18-3:
U-0 -- bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-6 bit 5 Unimplemented: Read as `0' VREGEN: USB Internal Voltage Regulator Enable bit 1 = USB voltage regulator enabled 0 = USB voltage regulator disabled BORV1:BORV0: Brown-out Reset Voltage bits(1) 11 = Minimum setting . . . 00 = Maximum setting BOREN1:BOREN0: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled See Section 21.0 "Electrical Characteristics" for the specifications. The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled.
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0 -- R/P-0 VREGEN R/P-1 BORV1(1) R/P-1 BORV0(1) R/P-1 BOREN1(2) R/P-1 BOREN0(2) R/P-1 PWRTEN(2) bit 0
bit 4-3
bit 2-1
bit 0
Note 1: 2:
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REGISTER 18-4:
U-0 -- bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-5 bit 4-1 Unimplemented: Read as `0' WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit)
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0 -- U-0 -- R/P-1 WDTPS3 R/P-1 WDTPS2 R/P-1 WDTPS1 R/P-1 WDTPS0 R/P-1 WDTEN bit 0
bit 0
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REGISTER 18-5:
R/P-1 MCLRE bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0 -- U-0 -- U-0 -- U-0 -- R/P-0 LPT1OSC R/P-1 PBADEN U-0 -- bit 0
MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR pin disabled Unimplemented: Read as `0' LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation PBADEN: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.) 1 = PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset Unimplemented: Read as `0'
bit 6-3 bit 2
bit 1
bit 0
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REGISTER 18-6:
R/P-1 DEBUG bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-0 XINST R/P-0 ICPRT(1) U-0 -- R/P-0 BBSIZ R/P-1 LVP U-0 -- R/P-1 STVREN bit 0
DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit(1) 1 = ICPORT enabled 0 = ICPORT disabled Unimplemented: Read as `0' BBSIZ: Boot Block Size Select bit 1 = 2 kW Boot Block size 0 = 1 kW Boot Block size LVP: Single-Supply ICSPTM Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled Unimplemented: Read as `0' STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1 bit 0
Note 1:
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REGISTER 18-7:
U-0 -- bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-2 bit 1 Unimplemented: Read as `0' CP1: Code Protection bit 1 = Block 1 (002000-003FFFh) is not code-protected 0 = Block 1 (002000-003FFFh) is code-protected CP0: Code Protection bit 1 = Block 0 (000800-001FFFh) or (001000-001FFFh) is not code-protected 0 = Block 0 (000800-001FFFh) or (001000-001FFFh) is code-protected
CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/C-1 CP1 R/C-1 CP0 bit 0
bit 0
REGISTER 18-8:
U-0 -- bit 7 Legend: R = Readable bit
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1 CPB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
C = Clearable bit
U = Unimplemented bit, read as `0' u = Unchanged from programmed state
-n = Value when device is unprogrammed bit 7 bit 6 Unimplemented: Read as `0'
CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) or (000000-000FFFh) is not code-protected 0 = Boot block (000000-0007FFh) or (000000-000FFFh) is code-protected Unimplemented: Read as `0'
bit 5-0
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REGISTER 18-9:
U-0 -- bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-2 bit 1 Unimplemented: Read as `0' WRT1: Write Protection bit 1 = Block 1 (002000-003FFFh) is not write-protected 0 = Block 1 (002000-003FFFh) is write-protected WRT0: Write Protection bit 1 = Block 0 (000800-001FFFh) or (001000-001FFFh) is not write-protected 0 = Block 0 (000800-001FFFh) or (001000-001FFFh) is write-protected
CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/C-1 WRT1 R/C-1 WRT0 bit 0
bit 0
REGISTER 18-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
U-0 -- bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7 bit 6 Unimplemented: Read as `0' WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0007FFh) or (000000-000FFFh) is not write-protected 0 = Boot block (000000-0007FFh) or (000000-000FFFh) is write-protected WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers (300000-3000FFh) are not write-protected 0 = Configuration registers (300000-3000FFh) are write-protected Unimplemented: Read as `0' This bit is read-only in normal execution mode; it can be written only in Program mode. R/C-1 WRTB R-1 WRTC(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 5
bit 4-0 Note 1:
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REGISTER 18-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0 -- bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-2 bit 1 Unimplemented: Read as `0' EBTR1: Table Read Protection bit 1 = Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks 0 = Block 1 (002000-003FFFh) is protected from table reads executed in other blocks EBTR0: Table Read Protection bit 1 = Block 0 (000800-001FFFh) or (001000-001FFFh) is not protected from table reads executed in other blocks 0 = Block 0 (000800-001FFFh) or (001000-001FFFh) is protected from table reads executed in other blocks U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/C-1 EBTR1 R/C-1 EBTR0 bit 0
bit 0
REGISTER 18-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0 -- bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7 bit 6 Unimplemented: Read as `0' EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0007FFh) or (000000-000FFFh) is not protected from table reads executed in other blocks 0 = Boot block (000000-0007FFh) or (000000-000FFFh) is protected from table reads executed in other blocks Unimplemented: Read as `0' R/C-1 EBTRB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 5-0
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REGISTER 18-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2450/4450 DEVICES
R DEV2 bit 7 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-5 DEV2:DEV0: Device ID bits 001 = PIC18F2450 000 = PIC18F4450 REV3:REV0: Revision ID bits These bits are used to indicate the device revision. R DEV1 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0
bit 4-0
REGISTER 18-14: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2450/4450 DEVICES
R DEV10(1) bit 7 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-0 R DEV9(1) R DEV8(1) R DEV7(1) R DEV6(1) R DEV5(1) R DEV4(1) R DEV3(1) bit 0
DEV10:DEV3: Device ID bits(1) These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify the part number. 0010 0100 = PIC18F2450/4450 devices These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence.
Note 1:
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18.2 Watchdog Timer (WDT)
For PIC18F2450/4450 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: a SLEEP or CLRWDT instruction is executed or a clock failure has occurred. . Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: When a CLRWDT instruction is executed, the postscaler count will be cleared.
18.2.1
CONTROL REGISTER
Register 18-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT.
FIGURE 18-1:
SWDTEN WDTEN INTRC Source
WDT BLOCK DIAGRAM
Enable WDT
INTRC Control Wake-up from Power-Managed Modes Programmable Postscaler 1:1 to 1:32,768 4 Reset WDT Reset
WDT Counter /128
CLRWDT All Device Resets
WDT WDTPS<3:0> SLEEP
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REGISTER 18-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SWDTEN(1) bit 0
Unimplemented: Read as `0' SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off This bit has no effect if the Configuration bit, WDTEN, is enabled.
Note 1:
TABLE 18-2:
Name RCON WDTCON
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 IPEN -- Bit 6 SBOREN(1) -- Bit 5 -- -- Bit 4 RI -- Bit 3 TO -- Bit 2 PD -- Bit 1 POR -- Bit 0 BOR SWDTEN Reset Values on page 50 50
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Watchdog Timer. Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as `0'.
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18.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit. Two-Speed Start-up should be enabled only if the primary oscillator mode is XT, HS, XTPLL or HSPLL (Crystal-based modes). Other sources do not require an OST start-up delay; for these, Two-Speed Start-up should be disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. Because the OSCCON register is cleared on Reset events, the INTRC clock is used directly at its base frequency. In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored.
18.3.1
SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial SLEEP instructions (refer to Section 3.1.4 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS1:SCS0 bit settings or issue SLEEP instructions before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator is providing the clock during wake-up from Reset or Sleep mode.
FIGURE 18-2:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTRC OSC1 TOST(1) PLL Clock Output TPLL(1) 1 2 n-1 n
Clock Transition CPU Clock Peripheral Clock Program Counter PC PC + 2 OSTS bit Set PC + 4 PC + 6
Wake from Interrupt Event Note 1:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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18.4 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. Clock monitoring (shown in Figure 18-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the device clock source, but cleared on the rising edge of the sample clock. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator fails, no failure would be detected, nor would any action be possible.
18.4.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock Monitor events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out.
FIGURE 18-3:
FSCM BLOCK DIAGRAM
Clock Monitor Latch (CM) (edge-triggered)
18.4.2
EXITING FAIL-SAFE OPERATION
Peripheral Clock INTRC Source (32 s) / 64 488 Hz (2.048 ms)
S
Q
C
Q
Clock Failure Detected
The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any startup delays that are required for the oscillator mode, such as OST or PLL timer). The INTRC provides the device clock until the primary clock source becomes ready (similar to a Two-Speed Start-up). The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTRC. The OSCCON register will remain in its Reset state until a power-managed mode is entered.
Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 18-4). This causes the following: * the FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>); * the device clock source is switched to the internal oscillator (OSCCON is not updated to show the current clock source - this is the fail-safe condition); and * the WDT is reset.
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FIGURE 18-4:
Sample Clock Device Clock Output CM Output (Q) Failure Detected OSCFIF Oscillator Failure
FSCM TIMING DIAGRAM
CM Test Note:
CM Test
CM Test
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
18.4.3
FSCM INTERRUPTS IN POWER-MANAGED MODES
By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-Safe Clock Monitoring of the powermanaged clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTRC. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTRC source.
considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator is automatically configured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: The same logic that prevents false oscillator failure interrupts on POR or wake from Sleep will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged.
18.4.4
POR OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or Low-Power Sleep mode. When the primary device clock is either EC or INTRC, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL or XT), the situation is somewhat different. Since the oscillator may require a start-up time
As noted in Section 18.3.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled.
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18.5 Program Verification and Code Protection
Each of the three blocks has three code protection bits associated with them. They are: * Code-Protect bit (CPn) * Write-Protect bit (WRTn) * External Block Table Read bit (EBTRn) Figure 18-5 shows the program memory organization for 24 and 32-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 18-3.
The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PICmicro(R) devices. The user program memory is divided into three blocks. One of these is a boot block of 1 or 2 Kbytes. The remainder of the memory is divided into two blocks on binary boundaries.
FIGURE 18-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2450/4450
MEMORY SIZE/DEVICE 16 Kbytes (PIC18F2450/4450) Boot Block Address Range 000000h 0007FFh 000FFFh 001000h Block 0 001FFFh 002000h Block 1 003FFFh Unimplemented Read `0's Unimplemented Read `0's CP1, WRT1, EBTR1 CP0, WRT0, EBTR0 Block Code Protection Controlled By:
CPB, WRTB, EBTRB
Unimplemented Read `0's
(Unimplemented Memory Space)
1FFFFFh
TABLE 18-3:
300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh
SUMMARY OF CODE PROTECTION REGISTERS
Bit 7 -- -- -- -- -- -- Bit 6 -- CPB -- WRTB -- EBTRB Bit 5 -- -- -- WRTC -- -- Bit 4 -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- Bit 1 CP1 -- WRT1 -- EBTR1 -- Bit 0 CP0 -- WRT0 -- EBTR0 --
File Name CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H
Legend: Shaded cells are unimplemented.
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18.5.1 PROGRAM MEMORY CODE PROTECTION
The program memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn Configuration bit is `0'. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to `0', a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading `0's. Figures207 through208 illustrate table write and table read protection. Note: Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full Chip Erase or Block Erase function. The full Chip Erase and Block Erase functions can only be initiated via ICSP operation or an external programmer.
FIGURE 18-6:
TABLE WRITE (WRTn) DISALLOWED
Program Memory 000000h 0007FFh 000FFFh 001000h Configuration Bit Settings WRTB, EBTRB = 11
Register Values
TBLPTR = 0008FFh PC = 001FFEh TBLWT* 001FFFh 002000h
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11 003FFFh WRT2, EBTR2 = 11
WRT3, EBTR3 = 11 Results: All table writes disabled to Blockn whenever WRTn = 0.
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FIGURE 18-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Program Memory 000000h 0007FFh 000FFFh 001000h TBLPTR = 0008FFh 001FFFh 002000h WRT1, EBTR1 = 11 PC = 003FFEh TBLRD* 003FFFh Configuration Bit Settings WRTB, EBTRB = 11 Register Values
WRT0, EBTR0 = 10
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of `0'.
FIGURE 18-8:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Program Memory 000000h 0007FFh 000FFFh 001000h Configuration Bit Settings WRTB, EBTRB = 11
Register Values
TBLPTR = 0008FFh PC = 001FFEh TBLRD*
WRT0, EBTR0 = 10 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh
Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR.
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18.5.2 CONFIGURATION REGISTER PROTECTION
The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP operation or an external programmer. To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP/RE3, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies.
18.9
18.6
ID Locations
Special ICPORT Features (Designated Packages Only)
Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions or during program/verify. The ID locations can be read when the device is code-protected.
Under specific circumstances, the No Connect (NC) pins of PIC18F4450 devices in 44-pin TQFP packages can provide additional functionality. These features are controlled by device Configuration bits and are available only in this package type and pin count.
18.9.1
DEDICATED ICD/ICSP PORT
18.7
In-Circuit Serial Programming
PIC18F2450/4450 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
The 44-pin TQFP devices can use NC pins to provide an alternate port for In-Circuit Debugging (ICD) and InCircuit Serial Programming (ICSP). These pins are collectively known as the dedicated ICSP/ICD port, since they are not shared with any other function of the device. When implemented, the dedicated port activates three NC pins to provide an alternate device Reset, data and clock ports. None of these ports overlap with standard I/O pins, making the I/O pins available to the user's application. The dedicated ICSP/ICD port is enabled by setting the ICPRT Configuration bit. The port functions the same way as the legacy ICSP/ICD port on RB6/RB7. Table 18-5 identifies the functionally equivalent pins for ICSP and ICD purposes.
18.8
In-Circuit Debugger
When the DEBUG Configuration bit is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 18-4 shows which resources are required by the background debugger.
TABLE 18-5:
EQUIVALENT PINS FOR LEGACY AND DEDICATED ICD/ICSPTM PORTS
Pin Type P Pin Function
Pin Name Legacy Port MCLR/VPP/ RE3 RB6/KBI2/ PGC RB7/KBI3/ PGD Legend: Dedicated Port NC/ICRST/ ICVPP NC/ICCK/ ICPGC NC/ICDT/ ICPGD
TABLE 18-4:
I/O pins: Stack:
DEBUGGER RESOURCES
RB6, RB7 2 levels 512 bytes 10 bytes
Program Memory: Data Memory:
Device Reset and Programming Enable Serial Clock Serial Data
I I/O
I = Input, O = Output, P = Power
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Even when the dedicated port is enabled, the ICSP and ICD functions remain available through the legacy port. When VIH is seen on the MCLR/VPP/RE3 pin, the state of the ICRST/ICVPP pin is ignored. Note 1: The ICPRT Configuration bit can only be programmed through the default ICSP port. 2: The ICPRT Configuration bit must be maintained clear for all 28-pin and 40-pin devices; otherwise, unexpected operation may occur. Note 1: High-Voltage Programming is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in Low-Voltage ICSP Programming mode, the RB5 pin can no longer be used as a general purpose I/O pin and should be held low during normal operation. 3: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 5 in the TRISB register must be cleared to disable the pull-up on RB5 and ensure the proper operation of the device. 4: If the device Master Clear is disabled, verify that either of the following is done to ensure proper entry into ICSP mode: a) disable Low-Voltage Programming (CONFIG4L<2> = 0); or b) make certain that RB5/KBI1/PGM is held low during entry into ICSP. If Single-Supply ICSP Programming mode will not be used, the LVP bit can be cleared. RB5/KBI1/PGM then becomes available as the digital I/O pin, RB5. The LVP bit may be set or cleared only when using standard high-voltage programming (VIHH applied to the MCLR/ VPP/RE3 pin). Once LVP has been disabled, only the standard high-voltage programming is available and must be used to program the device. Memory that is not code-protected can be erased using either a Block Erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a Block Erase is required. If a Block Erase is to be performed when using Low-Voltage Programming, the device must be supplied with VDD of 4.5V to 5.5V.
18.9.2
28-PIN EMULATION
PIC18F4450 devices in 44-pin TQFP packages also have the ability to change their configuration under external control for debugging purposes. This allows the device to behave as if it were a PIC18F2455/2550 28-pin device. This 28-pin Configuration mode is controlled through a single pin, NC/ICPORTS. Connecting this pin to VSS forces the device to function as a 28-pin device. Features normally associated with the 40/44-pin devices are disabled, along with their corresponding control registers and bits. On the other hand, connecting the pin to VDD forces the device to function in its default configuration. The configuration option is only available when background debugging and the dedicated ICD/ICSP port are both enabled (DEBUG Configuration bit is clear and ICPRT Configuration bit is set). When disabled, NC/ICPORTS is a No Connect pin.
18.10 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP Programming (formerly known as Low-Voltage ICSP Programming or LVP). When Single-Supply Programming is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP/RE3 pin, but the RB5/KBI1/ PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. While programming using Single-Supply Programming, VDD is applied to the MCLR/VPP/RE3 pin as in normal execution mode. To enter Programming mode, VDD is applied to the PGM pin.
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19.0 INSTRUCTION SET SUMMARY
The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 19-1 shows the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The Instruction Set Summary, shown in Table 19-2, lists the standard instructions recognized by the Microchip MPASMTM Assembler. Section 19.1.1 "Standard Instruction Set" provides a description of each instruction. PIC18F2450/4450 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of eight new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section.
19.1
Standard Instruction Set
The standard PIC18 instruction set adds many enhancements to the previous PICmicro instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16 bits) but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations
The PIC18 instruction set summary in Table 19-2 lists byte-oriented, bit-oriented, literal and control operations. Table 19-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a')
The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a')
The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located.
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TABLE 19-1:
Field a
OPCODE FIELD DESCRIPTIONS
Description RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). Bank Select Register. Used to select the current RAM bank. ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. Destination select bit d = 0: store result in WREG d = 1: store result in file register f Destination: either the WREG register or the specified register file location. 8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). 12-bit register file address (000h to FFFh). This is the source address. 12-bit register file address (000h to FFFh). This is the destination address. Global Interrupt Enable bit. Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). Label name. The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: No change to register (such as TBLPTR with table reads and writes) Post-Increment register (such as TBLPTR with table reads and writes) Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) The relative address (2's complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. Program Counter. Program Counter Low Byte. Program Counter High Byte. Program Counter High Byte Latch. Program Counter Upper Byte Latch. Power-Down bit. Product of Multiply High Byte. Product of Multiply Low Byte. Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) 21-bit Table Pointer (points to a program memory location). 8-bit Table Latch. Time-out bit. Top-of-Stack. Unused or unchanged. Watchdog Timer. Working register (accumulator). Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 7-bit offset value for indirect addressing of register files (source). 7-bit offset value for indirect addressing of register files (destination).
bbb BSR C, DC, Z, OV, N d
dest f fs fd GIE k label mm * *+ *+* n PC PCL PCH PCLATH PCLATU PD PRODH PRODL s
TBLPTR TABLAT TO TOS u WDT WREG x zs zd { } [text] (text) [expr] <> italics
Optional argument. Indicates an indexed address. The contents of text. Specifies bit n of the register indicated by the pointer expr. Assigned to. Register bit field. In the set of. User-defined term (font is Courier).
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FIGURE 19-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 15 10 OPCODE d 9 87 a f (FILE #) 0 ADDWF MYREG, W, B Example Instruction
d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 15 1111 12 11 f (Source FILE #) 0 f (Destination FILE #) 12 11 0 MOVFF MYREG1, MYREG2
OPCODE
f = 12-bit file register address Bit-oriented file register operations 15 12 11 98 7 f (FILE #) 0 BSF MYREG, bit, B
OPCODE b (BIT #) a
b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 12 11 n<19:8> (literal) 87 n<7:0> (literal) 0 0 GOTO Label 8 7 k (literal) 0 MOVLW 7Fh
n = 20-bit immediate value 15 OPCODE 15 1111 S = Fast bit 15 OPCODE 15 OPCODE 87 n<7:0> (literal) 11 10 n<10:0> (literal) 0 BC MYFUNC 0 BRA MYFUNC 12 11 n<19:8> (literal) 87 S n<7:0> (literal) 0 0 CALL MYFUNC
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TABLE 19-2:
Mnemonic, Operands
PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF Note 1: f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1
1, 2 1, 2
1, 2
ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N ffff None ffff None ffff Z, N
1, 2
1 0011 1 (2 or 3) 0110 1 0001
4 1, 2
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
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TABLE 19-2:
Mnemonic, Operands
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP Note 1: f, b, a f, b, a f, b, a f, b, a f, d, a n n n n n n n n n n, s -- -- n -- -- -- -- n s k s -- Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable Return with literal in WREG Return from Subroutine Go into Standby mode 1 1 1 (2 or 3) 1 (2 or 3) 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1001 1000 1011 1010 0111 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 bbba bbba bbba bbba bbba 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 ffff ffff ffff ffff ffff nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 ffff ffff ffff ffff ffff nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None None None None None None TO, PD C None 1, 2 1, 2 3, 4 3, 4 1, 2
CONTROL OPERATIONS
None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD
4
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
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TABLE 19-2:
Mnemonic, Operands LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: k k k f, k k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1000 1001 1010 1011 1100 1101 1110 1111 C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N None None None None None None None None
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
DATA MEMORY PROGRAM MEMORY OPERATIONS Table Read 2 Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write 2 Table Write with post-increment Table Write with post-decrement Table Write with pre-increment
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
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19.1.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
STANDARD INSTRUCTION SET
ADD Literal to W ADDLW 0 k 255 (W) + k W N, OV, C, DC, Z 0000 1111 kkkk kkkk Operation: Status Affected: Encoding: Description: k ADDWF Syntax: Operands: ADD W to f ADDWF 0 f 255 d [0,1] a [0,1] (W) + (f) dest N, OV, C, DC, Z 0010 01da ffff ffff f {,d {,a}}
The contents of W are added to the 8-bit literal `k' and the result is placed in W. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `k'
Q3 Process Data
Q4 Write to W
Example:
ADDLW
15h
Before Instruction W = 10h After Instruction W= 25h
Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' ADDWF 17h 0C2h 0D9h 0C2h
Q3 Process Data REG, 0, 0
Q4 Write to destination
Example: W = REG = After Instruction W REG = =
Before Instruction
Note:
All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
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ADDWFC Syntax: Operands: ADD W and Carry bit to f ADDWFC 0 f 255 d [0,1] a [0,1] (W) + (f) + (C) dest N, OV, C, DC, Z 0010 00da ffff ffff f {,d {,a}} ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' ANDLW A3h 03h Q3 Process Data 05Fh Q4 Write to W AND Literal with W ANDLW 0 k 255 (W) .AND. k W N, Z 0000 1011 kkkk kkkk k
Operation: Status Affected: Encoding: Description:
The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. 1 1
Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Example:
Before Instruction W = After Instruction W =
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' ADDWFC 1 02h 4Dh 0 02h 50h
Q3 Process Data REG, 0, 1
Q4 Write to destination
Example:
Before Instruction Carry bit = REG = W = After Instruction Carry bit = REG = W =
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ANDWF Syntax: Operands: AND W with f ANDWF 0 f 255 d [0,1] a [0,1] (W) .AND. (f) dest N, Z 0001 01da ffff ffff f {,d {,a}} BC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Carry BC n
-128 n 127 if Carry bit is `1' (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn
Operation: Status Affected: Encoding: Description:
The contents of W are ANDed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
If the Carry bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BC 5
Q4 Write to PC No operation Q4 No operation
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' ANDWF 17h C2h 02h C2h
Q3 Process Data REG, 0, 0
Q4 Write to destination
If No Jump: Q1 Decode
Example:
Before Instruction W = REG = After Instruction W = REG =
Example:
Before Instruction PC After Instruction If Carry PC If Carry PC
address (HERE) 1; address (HERE + 12) 0; address (HERE + 2)
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BCF Syntax: Operands: Bit Clear f BCF f, b {,a} BN Syntax: Operands: Operation: Status Affected: Encoding: bbba ffff ffff Description: Branch if Negative BN n
0 f 255 0b7 a [0,1] 0 f None 1001
-128 n 127 if Negative bit is `1' (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn
Operation: Status Affected: Encoding: Description:
Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
If the Negative bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BN Jump
Q4 Write to PC No operation Q4 No operation
Q2 Read register `f' BCF
Q3 Process Data FLAG_REG, C7h 47h
Q4 Write register `f' 7, 0
No operation If No Jump: Q1 Decode
Example:
Before Instruction FLAG_REG = After Instruction FLAG_REG =
Example:
Before Instruction PC After Instruction If Negative PC If Negative PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
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BNC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Carry BNC n BNN Syntax: Operands: Operation: Status Affected: 0011 nnnn nnnn Encoding: Description: Branch if Not Negative BNN n
-128 n 127 if Carry bit is `0' (PC) + 2 + 2n PC None 1110
-128 n 127 if Negative bit is `0' (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn
If the Carry bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
If the Negative bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNC Jump Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BNN Jump
Q4 Write to PC No operation Q4 No operation
Read literal `n' No operation
Read literal `n' HERE = = = = =
Example:
Example:
Before Instruction PC After Instruction If Carry PC If Carry PC
address (HERE) 0; address (Jump) 1; address (HERE + 2)
Before Instruction PC After Instruction If Negative PC If Negative PC
address (HERE) 0; address (Jump) 1; address (HERE + 2)
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BNOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Overflow BNOV n BNZ Syntax: Operands: Operation: Status Affected: 0101 nnnn nnnn Encoding: Description: Branch if Not Zero BNZ n
-128 n 127 if Overflow bit is `0' (PC) + 2 + 2n PC None 1110
-128 n 127 if Zero bit is `0' (PC) + 2 + 2n PC None 1110 0001 nnnn nnnn
If the Overflow bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
If the Zero bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNOV Jump address (HERE) 0; address (Jump) 1; address (HERE + 2) Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BNZ Jump
Q4 Write to PC No operation Q4 No operation
Read literal `n' No operation
Read literal `n' HERE = = = = =
Example:
Example:
Before Instruction PC After Instruction If Overflow PC If Overflow PC
Before Instruction PC After Instruction If Zero PC If Zero PC
address (HERE) 0; address (Jump) 1; address (HERE + 2)
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BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch BRA n BSF Syntax: Operands: Bit Set f BSF f, b {,a}
-1024 n 1023 (PC) + 2 + 2n PC None 1101 0nnn nnnn nnnn
0 f 255 0b7 a [0,1] 1 f None 1000 bbba ffff ffff
Operation: Status Affected: Encoding: Description:
Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2
Words: Cycles: Q Cycle Activity: Q1 Decode No operation
Q2 Read literal `n' No operation
Q3 Process Data No operation
Q4 Write to PC No operation Words: Cycles: Q Cycle Activity: Q1 Decode
Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q2 Read register `f' BSF = = Q3 Process Data Q4 Write register `f'
Example:
HERE = =
BRA
Jump
Before Instruction PC After Instruction PC
address (HERE) address (Jump) Example:
FLAG_REG, 7, 1 0Ah 8Ah
Before Instruction FLAG_REG After Instruction FLAG_REG
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BTFSC Syntax: Operands: Bit Test File, Skip if Clear BTFSC f, b {,a} 0 f 255 0b7 a [0,1] skip if (f) = 0 None 1011 bbba ffff ffff BTFSS Syntax: Operands: Bit Test File, Skip if Set BTFSS f, b {,a} 0 f 255 0b<7 a [0,1] skip if (f) = 1 None 1010 bbba ffff ffff
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction.
If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation BTFSS : : Q4 No operation Q4 No operation Q4 No operation No operation
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = = Q3 No operation Q3 No operation No operation BTFSC : : Q4 No operation Q4 No operation No operation Q2 Read register `f' Q3 Process Data Q4 No operation
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = = Q2 Read register `f'
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
FLAG, 1, 0
FLAG, 1, 0
Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC
address (HERE) 0; address (TRUE) 1; address (FALSE)
Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC
address (HERE) 0; address (FALSE) 1; address (TRUE)
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BTG Syntax: Operands: Bit Toggle f BTG f, b {,a} 0 f 255 0b<7 a [0,1] (f) f None 0111 bbba ffff ffff BOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Overflow BOV n
-128 n 127 if Overflow bit is `1' (PC) + 2 + 2n PC None 1110 0100 nnnn nnnn
Operation: Status Affected: Encoding: Description:
Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BOV Jump
Q4 Write to PC No operation Q4 No operation
Q2 Read register `f' BTG
Q3 Process Data PORTC, 4, 0
Q4 Write register `f'
Example:
Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h]
Example:
Before Instruction PC After Instruction If Overflow PC If Overflow PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
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BZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Zero BZ n CALL Syntax: Operands: Operation: Subroutine Call CALL k {,s} 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS None 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8
-128 n 127 if Zero bit is `1' (PC) + 2 + 2n PC None 1110 0000 nnnn nnnn
If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BZ Jump
Q4 Write to PC No operation Q4 No operation
Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `k'<7:0>, No operation HERE
Q3 Push PC to stack No operation CALL
Q4 Read literal `k'<19:8>, Write to PC No operation
Example:
Before Instruction PC After Instruction If Zero PC If Zero PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
No operation Example:
THERE,1
Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS =
address (HERE) address (THERE) address (HERE + 4) W BSR STATUS
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CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Clear f CLRF f {,a} CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD 0000 0000 0000 0100
0 f 255 a [0,1] 000h f, 1Z Z 0110 101a ffff ffff
Status Affected: Encoding: Description:
Clears the contents of the specified register. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 No operation CLRWDT = = = = = ?
Q3 Process Data
Q4 No operation
Words: Cycles: Q Cycle Activity: Q1 Decode
Example: Q2 Q3 Process Data FLAG_REG,1 5Ah 00h Q4 Write register `f'
Read register `f' CLRF = =
Example:
Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD
00h 0 1 1
Before Instruction FLAG_REG After Instruction FLAG_REG
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COMF Syntax: Operands: Complement f COMF f {,d {,a}} CPFSEQ Syntax: Operands: Operation: Compare f with W, Skip if f = W CPFSEQ 0 f 255 a [0,1] (f) - (W), skip if (f) = (W) (unsigned comparison) None 0110 001a ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation f {,a}
0 f 255 d [0,1] a [0,1] (f) dest N, Z 0001 11da ffff ffff
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Words: Q2 Read register `f' COMF 13h If skip: 13h ECh Q3 Process Data REG, 0, 0 Q4 Write to destination Cycles:
Example:
Before Instruction REG = After Instruction REG = W =
Q Cycle Activity: Q1 Decode
Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NEQUAL EQUAL = = = = = =
CPFSEQ REG, 0 : : HERE ? ? W; Address (EQUAL) W; Address (NEQUAL)
Before Instruction PC Address W REG After Instruction If REG PC If REG PC
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CPFSGT Syntax: Operands: Operation: Compare f with W, Skip if f > W CPFSGT 0 f 255 a [0,1] (f) - (W), skip if (f) > (W) (unsigned comparison) None 0110 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation f {,a} CPFSLT Syntax: Operands: Operation: Compare f with W, Skip if f < W CPFSLT 0 f 255 a [0,1] (f) - (W), skip if (f) < (W) (unsigned comparison) None 0110 000a ffff ffff f {,a}
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation Q4 No operation Q4 No operation Q4 No operation No operation
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE NLESS LESS = = < = = Q2 Read register `f'
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip:
If skip and followed by 2-word instruction:
Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NGREATER GREATER = = > = =
CPFSLT REG, 1 : : Address (HERE) ? W; Address (LESS) W; Address (NLESS)
CPFSGT REG, 0 : :
Before Instruction PC W After Instruction If REG PC If REG PC
Address (HERE) ? W; Address (GREATER) W; Address (NGREATER)
Before Instruction PC W After Instruction If REG PC If REG PC
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DAW Syntax: Operands: Operation: Decimal Adjust W Register DAW None If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> If [W<7:4> + DC > 9] or [C = 1] then (W<7:4>) + 6 + DC W<7:4>; else (W<7:4>) + DC W<7:4> Status Affected: Encoding: Description: C 0000 0000 0000 0111 DECF Syntax: Operands: Decrement f DECF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest C, DC, N, OV, Z 0000 01da ffff ffff
Operation: Status Affected: Encoding: Description:
DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 1 1 Words: Q2 Read register W DAW A5h 0 0 05h 1 0 Q3 Process Data Q4 Write W Cycles: Q Cycle Activity: Q1
Words: Cycles: Q Cycle Activity: Q1 Decode
Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q2 Read register `f' DECF 01h 0 00h 1 Q3 Process Data CNT, 1, 0 Q4 Write to destination
Example 1:
Decode
Before Instruction W = C = DC = After Instruction W = C = DC = Example 2: Before Instruction W = C = DC = After Instruction W = C = DC =
Example:
Before Instruction CNT = Z = After Instruction CNT = Z =
CEh 0 0 34h 1 0
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DECFSZ Syntax: Operands: Decrement f, Skip if 0 DECFSZ f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None 0010 11da ffff ffff DCFSNZ Syntax: Operands: Decrement f, Skip if Not 0 DCFSNZ 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None 0100 11da ffff ffff f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction.
Words: Cycles:
The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation DCFSNZ : : = = = = = ? TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) Q4 Write to destination Q4 No operation Q4 No operation No operation
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE CONTINUE Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) Q3 No operation Q3 No operation No operation DECFSZ GOTO Q4 No operation Q4 No operation No operation CNT, 1, 1 LOOP If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE ZERO NZERO Q2 Read register `f' Q3 Process Data Q4 Write to destination Q Cycle Activity: Q1 Decode Q2
Read register `f'
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
TEMP, 1, 0
Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC
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GOTO Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Unconditional Branch GOTO k 0 k 1048575 k PC<20:1> None 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Operation: Status Affected: Encoding: Description: INCF Syntax: Operands: Increment f INCF f {,d {,a}}
0 f 255 d [0,1] a [0,1] (f) + 1 dest C, DC, N, OV, Z 0010 10da ffff ffff
GOTO allows an unconditional branch anywhere within the entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. 2 2
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `k'<7:0>, No operation
Q3 No operation No operation
Q4 Read literal `k'<19:8>, Write to PC No operation Words: Cycles:
The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
No operation Example:
GOTO THERE
Q Cycle Activity: Q1 Decode Q2 Read register `f' INCF FFh 0 ? ? 00h 1 1 1 Q3 Process Data CNT, 1, 0 Q4 Write to destination
After Instruction PC = Address (THERE)
Example:
Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC =
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INCFSZ Syntax: Operands: Increment f, Skip if 0 INCFSZ 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None 0011 11da ffff ffff f {,d {,a}} INFSNZ Syntax: Operands: Increment f, Skip if Not 0 INFSNZ 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None 0100 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation INFSNZ Q4 Write to destination Q4 No operation Q4 No operation No operation f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. (default) If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction.
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE NZERO ZERO Q3 No operation Q3 No operation No operation INCFSZ : : Q4 No operation Q4 No operation No operation CNT, 1, 0 Q2 Read register `f' Q3 Process Data Q4 Write to destination
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE ZERO NZERO Q2 Read register `f'
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
REG, 1, 0
Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC =
Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO)
Before Instruction PC = After Instruction REG = If REG PC = If REG = PC =
Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO)
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IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR Literal with W IORLW k 0 k 255 (W) .OR. k W N, Z 0000 1001 kkkk kkkk Operation: Status Affected: Encoding: Description: IORWF Syntax: Operands: Inclusive OR W with f IORWF f {,d {,a}}
0 f 255 d [0,1] a [0,1] (W) .OR. (f) dest N, Z 0001 00da ffff ffff
The contents of W are ORed with the eight-bit literal `k'. The result is placed in W. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `k' IORLW 9Ah BFh
Q3 Process Data 35h
Q4 Write to W
Example:
Before Instruction W = After Instruction W =
Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' IORWF 13h 91h 13h 93h
Q3 Process Data RESULT, 0, 1
Q4 Write to destination
Example:
Before Instruction RESULT = W = After Instruction RESULT = W =
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LFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' MSB Read literal `k' LSB Q3 Process Data Process Data Q4 Write literal `k' MSB to FSRfH Write literal `k' to FSRfL Load FSR LFSR f, k 0f2 0 k 4095 k FSRf None 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Operation: Status Affected: Encoding: Description: MOVF Syntax: Operands: Move f MOVF f {,d {,a}}
0 f 255 d [0,1] a [0,1] f dest N, Z 0101 00da ffff ffff
The 12-bit literal `k' is loaded into the File Select Register pointed to by `f'. 2 2
Decode
Example: After Instruction FSR2H FSR2L
LFSR 2, 3ABh = = 03h ABh
The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' MOVF = = = =
Q3 Process Data REG, 0, 0 22h FFh 22h 22h
Q4 Write W
Example:
Before Instruction REG W After Instruction REG W
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MOVFF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move f to f MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None 1100 1111 ffff ffff ffff ffff ffffs ffffd MOVLB Syntax: Operands: Operation: Status Affected: Encoding: Description: Move Literal to Low Nibble in BSR MOVLW k 0 k 255 k BSR None 0000 0001 kkkk kkkk
The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. 2 2
The eight-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0' regardless of the value of k7:k4. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `k' MOVLB 02h 05h
Q3 Process Data 5
Q4 Write literal `k' to BSR
Example:
Before Instruction BSR Register = After Instruction BSR Register =
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' (src) No operation No dummy read
Q3 Process Data No operation
Q4 No operation Write register `f' (dest)
Decode
Example:
MOVFF = = = =
REG1, REG2 33h 11h 33h 33h
Before Instruction REG1 REG2 After Instruction REG1 REG2
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MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' MOVLW 5Ah Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' MOVWF 4Fh FFh 4Fh 4Fh Q3 Process Data REG, 0 Q4 Write register `f' Q3 Process Data 5Ah Q4 Write to W Move Literal to W MOVLW k 0 k 255 kW None 0000 1110 kkkk kkkk Operation: Status Affected: Encoding: Description: MOVWF Syntax: Operands: Move W to f MOVWF 0 f 255 a [0,1] (W) f None 0110 111a ffff ffff f {,a}
The eight-bit literal `k' is loaded into W. 1 1
Example: After Instruction W =
Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Example:
Before Instruction W = REG = After Instruction W = REG =
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MULLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply Literal with W MULLW k MULWF Syntax: Operands: Operation: 1101 kkkk kkkk Status Affected: Encoding: Description: Multiply W with f MULWF 0 f 255 a [0,1] (W) x (f) PRODH:PRODL None 0000 001a ffff ffff f {,a}
0 k 255 (W) x k PRODH:PRODL None 0000
An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A zero result is possible but not detected. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `k'
Q3 Process Data
Q4 Write registers PRODH: PRODL
Example: Before Instruction W PRODH PRODL After Instruction W PRODH PRODL
MULLW = = = = = =
0C4h E2h ? ? E2h ADh 08h Words: Cycles: Q Cycle Activity: Q1 Decode
An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A zero result is possible but not detected. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q2 Read register `f' Q3 Process Data Q4 Write registers PRODH: PRODL
Example: Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL
MULWF = = = = = = = =
REG, 1 C4h B5h ? ? C4h B5h 8Ah 94h
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NEGF Syntax: Operands: Operation: Status Affected: Encoding: Description: Negate f NEGF f {,a} NOP Syntax: Operands: Operation: Status Affected: Encoding: ffff ffff Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 No operation Q3 No operation Q4 No operation 110a No Operation NOP None No operation None 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx
0 f 255 a [0,1] (f) + 1 f N, OV, C, DC, Z 0110
Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
No operation. 1 1
Example: None.
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' NEGF
Q3 Process Data REG, 1
Q4 Write register `f'
Example:
Before Instruction REG = After Instruction REG =
0011 1010 [3Ah] 1100 0110 [C6h]
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POP Syntax: Operands: Operation: Status Affected: Encoding: Description: Pop Top of Return Stack POP None (TOS) bit bucket None 0000 0000 0000 0110 PUSH Syntax: Operands: Operation: Status Affected: Encoding: Description: Push Top of Return Stack PUSH None (PC + 2) TOS None 0000 0000 0000 0101
The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1
The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. 1 1
Words: Cycles: Q Cycle Activity: Q1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Push PC + 2 onto return stack PUSH = =
Q3 No operation
Q4 No operation
Q2 No operation POP GOTO
Q3 Pop TOS value
Q4 No operation
Decode
Example:
Example: NEW = = 0031A2h 014332h
Before Instruction TOS Stack (1 level down) After Instruction TOS PC
Before Instruction TOS PC After Instruction PC TOS Stack (1 level down)
345Ah 0124h
= =
014332h NEW
= = =
0126h 0126h 345Ah
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RCALL Syntax: Operands: Operation: Status Affected: Encoding: Description: Relative Call RCALL n RESET Syntax: Operands: Operation: Status Affected: 1nnn nnnn nnnn Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Start Reset RESET Reset Value Reset Value Q3 No operation Q4 No operation Reset RESET None Reset all registers and flags that are affected by a MCLR Reset. All 0000 0000 1111 1111
-1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None 1101
Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2
This instruction provides a way to execute a MCLR Reset in software. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Example: Q2 Q3 Process Data Q4 Write to PC After Instruction Registers = Flags* =
Read literal `n' Push PC to stack
No operation Example:
No operation HERE
No operation RCALL Jump
No operation
Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2)
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RETFIE Syntax: Operands: Operation: Return from Interrupt RETFIE {s} s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged GIE/GIEH, PEIE/GIEL. 0000 0000 0001 000s RETLW Syntax: Operands: Operation: Return Literal to W RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None 0000 1100 kkkk kkkk
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2
W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `k' No operation
Q3 Process Data No operation
Q4 Pop PC from stack, Write to W No operation
Words: Cycles: Q Cycle Activity: Q1 Decode
No operation Example: Q2 Q3 No operation Q4 Pop PC from stack Set GIEH or GIEL
No operation
No operation Example:
No operation RETFIE 1
No operation
No operation
After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL
= = = = =
TOS WS BSRS STATUSS 1
CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W =
W contains table offset value W now has table value
W = offset Begin table
End of table
07h value of kn
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RETURN Syntax: Operands: Operation: Return from Subroutine RETURN {s} s [0,1] (TOS) PC, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None 0000 0000 0001 001s RLCF Syntax: Operands: Rotate Left f through Carry RLCF f {,d {,a}}
0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) C, (C) dest<0> C, N, Z 0011 01da ffff ffff
Operation:
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2
Words: Cycles: Q Cycle Activity: Q1 Decode No operation
Q2 No operation No operation
Q3 Process Data No operation
Q4 Pop PC from stack No operation Words: Cycles: Q Cycle Activity:
The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. C 1 1 register f
Example:
RETURN
Q1 Decode
Q2 Read register `f' RLCF
Q3 Process Data
Q4 Write to destination
After Instruction: PC = TOS
Example: Before Instruction REG = C = After Instruction REG = W = C =
REG, 0, 0
1110 0110 0 1110 0110 1100 1100 1
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RLNCF Syntax: Operands: Rotate Left f (No Carry) RLNCF 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) dest<0> N, Z 0100 01da ffff ffff Status Affected: Encoding: Description: f {,d {,a}} RRCF Syntax: Operands: Rotate Right f through Carry RRCF f {,d {,a}}
0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) C, (C) dest<7> C, N, Z 0011 00da ffff ffff
Operation: Status Affected: Encoding: Description:
Operation:
The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f
The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. C register f
Words: Cycles: Q Cycle Activity: Q1 Decode
1 1 Words: Q2 Read register `f' RLNCF Q3 Process Data Q4 Write to destination Cycles: Q Cycle Activity: Q1 Decode Q2 1 1
Q3 Process Data REG, 0, 0
Q4 Write to destination
Example: Before Instruction REG = After Instruction REG =
REG, 1, 0 Example:
Read register `f' RRCF
1010 1011 0101 0111
Before Instruction REG = C = After Instruction REG = W = C =
1110 0110 0 1110 0110 0111 0011 0
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RRNCF Syntax: Operands: Rotate Right f (No Carry) RRNCF f {,d {,a}} SETF Syntax: Operands: Operation: Status Affected: Encoding: ffff ffff Description: Set f SETF f {,a}
0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) dest<7> N, Z 0100 00da
0 f 255 a [0,1] FFh f None 0110 100a ffff ffff
Operation: Status Affected: Encoding: Description:
The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f
The contents of the specified register are set to FFh. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' SETF = = 5Ah FFh
Q3 Process Data REG,1
Q4 Write register `f'
Words: Cycles: Q Cycle Activity: Q1 Decode
1 1 Q2 Read register `f' RRNCF Q3 Process Data REG, 1, 0 Q4 Write to destination Example:
Before Instruction REG After Instruction REG
Example 1:
Before Instruction REG = After Instruction REG = Example 2:
1101 0111 1110 1011 REG, 0, 0
RRNCF
Before Instruction W = REG = After Instruction W = REG =
? 1101 0111 1110 1011 1101 0111
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SLEEP Syntax: Operands: Operation: Enter Sleep mode SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD 0000 0000 0000 0011 SUBFWB Syntax: Operands: Subtract f from W with Borrow SUBFWB 0 f 255 d [0,1] a [0,1] (W) - (f) - (C) dest N, OV, C, DC, Z 0101 01da ffff ffff f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 No operation SLEEP
Q3 Process Data
Q4 Go to Sleep Words: Cycles: Q Cycle Activity: Q1 Decode
Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q2 Read register `f' Q3 Process Data Q4 Write to destination
Example: Before Instruction TO = ? ? PD =
After Instruction 1 TO = 0 PD = If WDT causes wake-up, this bit is cleared.
SUBFWB REG, 1, 0 Example 1: Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative SUBFWB REG, 0, 0 Example 2: Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive SUBFWB REG, 1, 0 Example 3: Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0
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SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description Words: Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = Q2 Read literal `k' SUBLW 01h ? 01h 1 0 0 SUBLW 02h ? 00h 1 1 0 SUBLW 03h ? FFh 0 0 1 ; (2's complement) ; result is negative ; result is zero Example 1: 02h Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = ; result is positive Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' SUBWF 3 2 ? 1 2 1 0 0 SUBWF 2 2 ? 2 0 1 1 0 SUBWF 1 2 ? FFh ;(2's complement) 2 0 ; result is negative 0 1 Q3 Process Data REG, 1, 0 Q4 Write to destination Q3 Process Data 02h Q4 Write to W Subtract W from Literal SUBLW k 0 k 255 k - (W) W N, OV, C, DC, Z 0000 1000 kkkk kkkk Operation: Status Affected: Encoding: Description: SUBWF Syntax: Operands: Subtract W from f SUBWF 0 f 255 d [0,1] a [0,1] (f) - (W) dest N, OV, C, DC, Z 0101 11da ffff ffff f {,d {,a}}
W is subtracted from the eight-bit literal `k'. The result is placed in W. 1 1
Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
02h
; result is positive
REG, 0, 0
; result is zero
REG, 1, 0
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SUBWFB Syntax: Operands: Subtract W from f with Borrow SUBWFB 0 f 255 d [0,1] a [0,1] (f) - (W) - (C) dest N, OV, C, DC, Z 0101 10da ffff ffff Status Affected: Encoding: Description: Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q2 Read register `f' SUBWFB 19h 0Dh 1 0Ch 0Dh 1 0 0 Q3 Process Data REG, 1, 0 (0001 1001) (0000 1101) Example: Q4 Write to destination Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' SWAPF 53h 35h Q3 Process Data REG, 1, 0 Q4 Write to destination f {,d {,a}} SWAPF Syntax: Operands: Swap f SWAPF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None 0011 10da ffff ffff
Operation: Status Affected: Encoding: Description:
Operation:
Words: Cycles: Q Cycle Activity: Q1 Decode Example 1:
The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W C Z N = = = =
(0000 1011) (0000 1101) ; result is positive
Before Instruction REG = After Instruction REG =
SUBWFB REG, 0, 0 1Bh 1Ah 0 1Bh 00h 1 1 0 SUBWFB 03h 0Eh 1 F5h 0Eh 0 0 1 (0001 1011) (0001 1010) (0001 1011) ; result is zero REG, 1, 0 (0000 0011) (0000 1101) (1111 0100) ; [2's comp] (0000 1101) ; result is negative
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TBLRD Syntax: Operands: Operation: Table Read TBLRD ( *; *+; *-; +*) None if TBLRD * (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+ (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *(Prog Mem (TBLPTR)) TABLAT; (TBLPTR) - 1 TBLPTR; if TBLRD +* (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT TBLRD Example 1: Table Read (Continued) TBLRD *+ ; = = = = = 55h 00A356h 34h 34h 00A357h
Before Instruction TABLAT TBLPTR MEMORY (00A356h) After Instruction TABLAT TBLPTR Example 2: TBLRD
+* ; = = = = = = AAh 01A357h 12h 34h 34h 01A358h
Status Affected: None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +*
Before Instruction TABLAT TBLPTR MEMORY (01A357h) MEMORY (01A358h) After Instruction TABLAT TBLPTR
Description:
This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2
Words: Cycles: Q Cycle Activity: Q1 Decode No operation
Q2 No operation No operation (Read Program Memory)
Q3 No operation No operation
Q4 No operation No operation (Write TABLAT)
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TBLWT Syntax: Operands: Operation: Table Write TBLWT ( *; *+; *-; +*) None if TBLWT* (TABLAT) Holding Register; TBLPTR - No Change; if TBLWT*+ (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR; if TBLWT*(TABLAT) Holding Register; (TBLPTR) - 1 TBLPTR; if TBLWT+* (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* TBLWT Example 1: Table Write (Continued) TBLWT *+;
Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: TBLWT +*;
Status Affected: None Encoding:
Description:
This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 "Flash Program Memory" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2 Q1 Decode Q2 Q3 Q4
Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h
Words: Cycles: Q Cycle Activity:
No No No operation operation operation
No No No No operation operation operation operation (Read (Write to TABLAT) Holding Register)
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TSTFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Test f, Skip if 0 TSTFSZ f {,a} 0 f 255 a [0,1] skip if f = 0 None 0110 011a ffff ffff XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W XORLW k 0 k 255 (W) .XOR. k W N, Z 0000 1010 kkkk kkkk
If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction.
The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. 1 1
Words: Cycles: Q Cycle Activity:
Q1
Decode
Q2
Read literal `k' XORLW B5h 1Ah
Q3
Process Data 0AFh
Q4
Write to W
Example: Before Instruction W = After Instruction W =
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE NZERO ZERO = = = = Q3 No operation Q3 No operation No operation TSTFSZ : : Q4 No operation Q4 No operation No operation Q2 Read register `f' Q3 Process Data Q4 No operation
If skip and followed by 2-word instruction:
CNT, 1
Before Instruction PC After Instruction If CNT PC If CNT PC
Address (HERE) 00h, Address (ZERO) 00h, Address (NZERO)
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XORWF Syntax: Operands: Exclusive OR W with f XORWF 0 f 255 d [0,1] a [0,1] (W) .XOR. (f) dest N, Z 0001 10da ffff ffff f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 19.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' XORWF AFh B5h 1Ah B5h
Q3 Process Data REG, 1, 0
Q4 Write to destination
Example:
Before Instruction REG = W = After Instruction REG = W =
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19.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2450/4450 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST Configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for Indexed Addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: * Dynamic allocation and deallocation of software stack space when entering and leaving subroutines * Function Pointer invocation * Software Stack Pointer manipulation * Manipulation of variables located in a software stack A summary of the instructions in the extended instruction set is provided in Table 19-3. Detailed descriptions are provided in Section 19.2.2 "Extended Instruction Set". The opcode field descriptions in Table 19-1 (page 212) apply to both the standard and extended PIC18 instruction sets. Note: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler.
19.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of Indexed Addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the argument is used as an index or offset. The MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. When the extended instruction set is enabled, brackets are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 19.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands". Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }").
TABLE 19-3:
Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR SUBULNK f, k k
EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word Description Add literal to FSR Add literal to FSR2 and return Call subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store literal at FSR2, decrement FSR2 Subtract literal from FSR Subtract literal from FSR2 and return Cycles MSb 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk LSb kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk Status Affected None None None None None None None None
zs, fd zs, zd k f, k k
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19.2.2
ADDFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' Q3 Process Data Q4 Write to FSR
EXTENDED INSTRUCTION SET
Add Literal to FSR ADDFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) + k FSR(f) None 1110 1000 ffkk kkkk The 6-bit literal `k' is added to the contents of the FSR specified by `f'. 1 1 Status Affected: Encoding: Description: ADDULNK Syntax: Operands: Operation: Add Literal to FSR2 and Return ADDULNK k 0 k 63 FSR2 + k FSR2, (TOS) PC None 1110 1000 11kk kkkk The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2 Q1 0422h Decode No Operation Q2 Read literal `k' No Operation Q3 Process Data No Operation Q4 Write to FSR No Operation
Example:
ADDFSR 03FFh
2, 23h
Words: Cycles: Q Cycle Activity:
Before Instruction FSR2 = After Instruction FSR2 =
Example:
ADDULNK 23h 03FFh 0100h 0422h (TOS)
Before Instruction FSR2 = PC = After Instruction FSR2 = PC =
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
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CALLW Syntax: Operands: Operation: Subroutine Call Using WREG CALLW None (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU None 0000 0000 0001 0100 MOVSF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move Indexed to f MOVSF [zs], fd 0 zs 127 0 fd 4095 ((FSR2) + zs) fd None 1110 1111 1011 ffff 0zzz ffff zzzzs ffffd
Status Affected: Encoding: Description
First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, STATUS or BSR. 1 2
Words: Cycles: Q Cycle Activity: Q1 Decode No operation
Q2 Read WREG No operation
Q3 Push PC to stack No operation
Q4 No operation No operation Words: Cycles: Q Cycle Activity: Q1 Decode
The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs' in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. 2 2 Q2 Q3 Q4 Read source reg Write register `f' (dest)
Example:
HERE
CALLW Decode
Determine Determine source addr source addr No operation No dummy read No operation
Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W =
address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h Example:
MOVSF = = = = = =
[05h], REG2 80h 33h 11h 80h 33h 33h
Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2
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MOVSS Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (dest.) Description Move Indexed to Indexed MOVSS [zs], [zd] 0 zs 127 0 zd 127 ((FSR2) + zs) ((FSR2) + zd) None 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd PUSHL Syntax: Operands: Operation: Status Affected: Encoding: Description: Store Literal at FSR2, Decrement FSR2 PUSHL k 0 k 255 k (FSR2), FSR2 - 1 FSR2 None 1111 1010 kkkk kkkk
The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. 2 2
The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by `1' after the operation. This instruction allows users to push values onto a software stack. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read `k'
Q3 Process data
Q4 Write to destination
Example:
PUSHL
08h = = 01ECh 00h
Before Instruction FSR2H:FSR2L Memory (01ECh) After Instruction FSR2H:FSR2L Memory (01ECh)
Words: Cycles: Q Cycle Activity: Q1 Decode Decode
= =
01EBh 08h
Q2
Q3
Q4 Read source reg Write to dest reg
Determine Determine source addr source addr Determine dest addr Determine dest addr
Example:
MOVSS = = = = = =
[05h], [06h] 80h 33h 11h 80h 33h 33h
Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h
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SUBFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract Literal from FSR SUBFSR f, k 0 k 63 f [ 0, 1, 2 ] FSRf - k FSRf None 1110 1001 ffkk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. 1 1 Q1 Decode Q2 Read register `f' Q3 Process Data Q4 Write to destination Words: Cycles: Example: Before Instruction FSR2 = After Instruction FSR2 = SUBFSR 2, 23h 03FFh 03DCh Q1 Decode No Operation Encoding: Description: SUBULNK Syntax: Operands: Operation: Subtract Literal from FSR2 and Return SUBULNK k 0 k 63 FSR2 - k FSR2 (TOS) PC Status Affected: None 1110 1001 11kk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2 Q2 Read register `f' No Operation Q3 Process Data No Operation Q4 Write to destination No Operation
Words: Cycles: Q Cycle Activity:
Q Cycle Activity:
Example: Before Instruction FSR2 = PC = After Instruction FSR2 = PC =
SUBULNK 23h 03FFh 0100h 03DCh (TOS)
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19.2.3 BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely.
19.2.3.1
Extended Instruction Syntax with Standard PIC18 Commands
Note:
In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.6.1 "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (`a' = 0) or in a GPR bank designated by the BSR (`a' = 1). When the extended instruction set is enabled and `a' = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all byteoriented and bit-oriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 19.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands"). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types.
When the extended instruction set is enabled, the file register argument, `f', in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing mode, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled) when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument, `d', functions as before. In the latest versions of the MPASM assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing.
19.2.4
CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F2450/4450, it is very important to consider the type of code. A large, re-entrant application that is written in `C' and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set.
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ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description: ADD W to Indexed (Indexed Literal Offset mode) ADDWF 0 k 95 d [0,1] (W) + ((FSR2) + k) dest N, OV, C, DC, Z 0010 01d0 kkkk kkkk [k] {,d} BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' BSF = = = Q3 Process Data Q4 Write to destination Bit Set Indexed (Indexed Literal Offset mode) BSF [k], b 0 f 95 0b7 1 ((FSR2) + k) None 1000 bbb0 kkkk kkkk
The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). 1 1
Bit `b' of the register indicated by FSR2, offset by the value `k', is set. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read `k'
Q3 Process Data [OFST] ,0 = = = = = = 17h 2Ch 0A00h 20h 37h 20h
Q4 Write to destination
Example:
[FLAG_OFST], 7 0Ah 0A00h 55h
Example:
ADDWF
Before Instruction W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch
Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah
=
D5h
SETF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
Set Indexed (Indexed Literal Offset mode) SETF [k] 0 k 95 FFh ((FSR2) + k) None 0110 1000 kkkk kkkk
The contents of the register indicated by FSR2, offset by `k', are set to FFh. 1 1 Q2 Read `k' Q3 Process Data [OFST] 2Ch 0A00h 00h Q4 Write register
Example:
SETF = = =
Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch
=
FFh
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19.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB(R) IDE TOOLS
To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: * A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project * A command line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information.
The latest versions of Microchip's software tools have been designed to fully support the extended instruction set of the PIC18F2450/4450 family of devices. This includes the MPLAB C18 C compiler, MPASM Assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is `0', disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming.
DS39760A-page 260
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PIC18F2450/4450
20.0 DEVELOPMENT SUPPORT
20.1
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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20.2 MPASM Assembler 20.5
The MPASM Assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
20.6 20.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 family of microcontrollers and dsPIC30F family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PICmicro MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, as well as internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
20.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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PIC18F2450/4450
20.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 20.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost-effective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
20.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
20.8
MPLAB ICE 4000 High-Performance In-Circuit Emulator
The MPLAB ICE 4000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high-end PICmicro MCUs and dsPIC DSCs. Software control of the MPLAB ICE 4000 In-Circuit Emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, and up to 2 Mb of emulation memory. The MPLAB ICE 4000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
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PIC18F2450/4450
20.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PICmicro devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
20.12 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PICmicro MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
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PIC18F2450/4450
21.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
Ambient temperature under bias.............................................................................................................. .-40C to +85C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS.
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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DS39760A-page 265
PIC18F2450/4450
FIGURE 21-1: PIC18F2450/4450 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V PIC18F2450/4450 4.2V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
48 MHz
Frequency
FIGURE 21-2:
PIC18LF2450/4450 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V 4.5V 4.0V 4.2V
PIC18LF2450/4450
Voltage
3.5V 3.0V 2.5V 2.0V
4 MHz
16 MHz
25 MHz
48 MHz
Frequency
Note: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application.
DS39760A-page 266
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PIC18F2450/4450
21.1 DC Characteristics: Supply Voltage PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min 2.0 3.0 Typ -- -- Max Units 5.5 5.5 V V Conditions EC, HS, XT and Internal Oscillator modes HSPLL, XTPLL, ECPIO and ECPLL Oscillator modes
PIC18LF2450/4450 (Industrial) PIC18F2331/2431/4331/4431 (Industrial) Param No. D001 Symbol VDD Characteristic Supply Voltage
RAM Data Retention 1.5 -- -- V Voltage(1) VDD Start Voltage -- -- 0.7 V See Section 4.3 "Power-on Reset (POR)" D003 VPOR to ensure internal Power-on for details Reset signal D004 SVDD VDD Rise Rate 0.05 -- -- V/ms See Section 4.3 "Power-on Reset (POR)" to ensure internal Power-on for details Reset signal D005 VBOR Brown-out Reset Voltage BORV1:BORV0 = 11 2.00 2.05 2.16 V BORV1:BORV0 = 10 2.65 2.79 2.93 V BORV1:BORV0 = 01 4.11 4.33 4.55 V BORV1:BORV0 = 00 4.36 4.59 4.82 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. D002 VDR
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21.2 DC Characteristics: Power-Down and Supply Current PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions
PIC18LF2450/4450 (Industrial) PIC18F2450/4450 (Industrial) Param No.
Legend: Note 1:
2:
3: 4:
Power-Down Current (IPD)(1) PIC18F2450/4450 0.1 TBD A -40C VDD = 2.0V 0.1 TBD A +25C (Sleep mode) 0.2 TBD A +85C PIC18LF2450/4450 0.1 TBD A -40C VDD = 3.0V 0.1 TBD A +25C (Sleep mode) 0.3 TBD A +85C All devices 0.1 TBD A -40C VDD = 5.0V 0.1 TBD A +25C (Sleep mode) 0.4 TBD A +85C TBD = To Be Determined. Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
DS39760A-page 268
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PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) PIC18LF2450/4450 Typ Max Units Conditions
PIC18LF2450/4450 (Industrial) PIC18F2450/4450 (Industrial) Param No.
15 15 15 40 35 30 105 90 80
TBD TBD TBD TBD TBD TBD TBD TBD TBD
A A A A A A A A A
-40C +25C +85C -40C +25C +85C -40C +25C +85C
VDD = 2.0V FOSC = 31 kHz (RC_RUN mode, INTRC source)
PIC18LF2450/4450
VDD = 3.0V
All devices
VDD = 5.0V
Legend: Note 1:
2:
3: 4:
TBD = To Be Determined. Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
(c) 2006 Microchip Technology Inc.
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PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) PIC18LF2450/4450 Typ Max Units Conditions
PIC18LF2450/4450 (Industrial) PIC18F2450/4450 (Industrial) Param No.
2.9 3.1 3.6 4.5 4.8 5.8 9.2
TBD TBD TBD TBD TBD TBD TBD
A A A A A A A
-40C +25C +85C -40C +25C +85C -40C
VDD = 2.0V FOSC = 31 kHz (RC_IDLE mode, INTRC source)
PIC18LF2450/4450
VDD = 3.0V
All devices
Legend: Note 1:
2:
3: 4:
VDD = 5.0V 9.8 TBD A +25C 11.4 TBD A +85C TBD = To Be Determined. Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
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PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) PIC18LF2450/4450 Typ Max Units Conditions
PIC18LF2450/4450 (Industrial) PIC18F2450/4450 (Industrial) Param No.
Legend: Note 1:
2:
3: 4:
FOSC = 1 MHZ (PRI_RUN, 480 TBD A +25C VDD = 3.0V EC oscillator) 460 TBD A +85C All devices 1.2 TBD mA -40C VDD = 5.0V 1.1 TBD mA +25C 1.0 TBD mA +85C PIC18LF2450/4450 0.74 TBD mA -40C VDD = 2.0V 0.74 TBD mA +25C 0.74 TBD mA +85C PIC18LF2450/4450 1.3 TBD mA -40C FOSC = 4 MHz (PRI_RUN, VDD = 3.0V 1.3 TBD mA +25C EC oscillator) 1.3 TBD mA +85C All devices 2.7 TBD mA -40C 2.6 TBD mA +25C VDD = 5.0V 2.5 TBD mA +85C All devices 15 TBD mA -40C 16 TBD mA +25C VDD = 4.2V FOSC = 40 MHZ 16 TBD mA +85C (PRI_RUN, All devices 21 TBD mA -40C EC oscillator) 21 TBD mA +25C VDD = 5.0V 21 TBD mA +85C All devices 20 TBD mA -40C 20 TBD mA +25C VDD = 4.2V FOSC = 48 MHZ 20 TBD mA +85C (PRI_RUN, All devices 25 TBD mA -40C EC oscillator) 25 TBD mA +25C VDD = 5.0V 25 TBD mA +85C TBD = To Be Determined. Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
PIC18LF2450/4450
250 250 250 550
TBD TBD TBD TBD
A A A A
-40C +25C +85C -40C
VDD = 2.0V
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21.2 DC Characteristics: Power-Down and Supply Current PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) 65 TBD A -40C VDD = 2.0V 65 TBD A +25C 70 TBD A +85C PIC18LF2450/4450 120 TBD A -40C FOSC = 1 MHz VDD = 3.0V (PRI_IDLE mode, 120 TBD A +25C EC oscillator) 130 TBD A +85C All devices 230 TBD A -40C VDD = 5.0V 240 TBD A +25C 250 TBD A +85C PIC18LF2450/4450 255 TBD A -40C VDD = 2.0V 260 TBD A +25C 270 TBD A +85C PIC18LF2450/4450 420 TBD A -40C FOSC = 4 MHz VDD = 3.0V (PRI_IDLE mode, 430 TBD A +25C EC oscillator) 450 TBD A +85C All devices 0.9 TBD mA -40C VDD = 5.0V 0.9 TBD mA +25C 0.9 TBD mA +85C All devices 6.0 TBD mA -40C 6.2 TBD mA +25C VDD = 4.2V FOSC = 40 MHz 6.6 TBD mA +85C (PRI_IDLE mode, All devices 8.1 TBD mA -40C EC oscillator) VDD = 5.0V 8.3 TBD mA +25C 9.0 TBD mA +85C All devices 8.0 TBD mA -40C 8.1 TBD mA +25C VDD = 4.2V FOSC = 48 MHz 8.2 TBD mA +85C (PRI_IDLE mode, All devices 9.8 TBD mA -40C EC oscillator) VDD = 5.0V 10.0 TBD mA +25C 10.5 TBD mA +85C TBD = To Be Determined. Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. PIC18LF2450/4450 Typ Max Units Conditions
PIC18LF2450/4450 (Industrial) PIC18F2450/4450 (Industrial) Param No.
Legend: Note 1:
2:
3: 4:
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PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) PIC18LF2450/4450 Typ Max Units Conditions
PIC18LF2450/4450 (Industrial) PIC18F2450/4450 (Industrial) Param No.
14 15 16 40 35 31 99
TBD TBD TBD TBD TBD TBD TBD
A A A A A A A
-40C +25C +85C -40C +25C +85C -40C
VDD = 2.0V FOSC = 32 kHz(3) (SEC_RUN mode, Timer1 as clock)
PIC18LF2450/4450
VDD = 3.0V
All devices
Legend: Note 1:
2:
3: 4:
VDD = 5.0V 81 TBD A +25C 75 TBD A +85C PIC18LF2450/4450 2.5 TBD A -40C VDD = 2.0V 3.7 TBD A +25C 4.5 TBD A +85C PIC18LF2450/4450 5.0 TBD A -40C FOSC = 32 kHz(3) 5.4 TBD A +25C VDD = 3.0V (SEC_IDLE mode, Timer1 as clock) 6.3 TBD A +85C All devices 8.5 TBD A -40C VDD = 5.0V 9.0 TBD A +25C 10.5 TBD A +85C TBD = To Be Determined. Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
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PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions
PIC18LF2450/4450 (Industrial) PIC18F2450/4450 (Industrial) Param No. D022 (IWDT)
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) Watchdog Timer 1.3 TBD A -40C 1.4 TBD A +25C 2.0 1.9 2.0 2.8 4.0 5.5 5.6 35 40 0 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A A A A A A A A A A +85C -40C +25C +85C -40C +25C +85C -40C to +85C -40C to +85C -40C to +85C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V VDD = 3.0V VDD = 5.0V Sleep mode, BOREN1:BOREN0 = 10
D022A (IBOR)
Brown-out Reset(4)
D022B (ILVD) D025 (IOSCB)
D026 (IAD) Legend: Note 1:
2:
3: 4:
22 TBD A -40C to +85C VDD = 2.0V 25 TBD A -40C to +85C VDD = 3.0V 29 TBD A -40C to +85C VDD = 5.0V Timer1 Oscillator 2.1 TBD A -40C VDD = 2.0V 1.8 TBD A +25C 32 kHz on Timer1(3) 2.1 TBD A +85C 2.2 TBD A -40C VDD = 3.0V 2.6 TBD A +25C 32 kHz on Timer1(3) 2.9 TBD A +85C 3.0 TBD A -40C VDD = 5.0V 3.2 TBD A +25C 32 kHz on Timer1(3) 3.4 TBD A +85C A/D Converter 1.0 TBD A -40C to +85C VDD = 2.0V 1.0 TBD A -40C to +85C VDD = 3.0V A/D on, not converting 1.0 TBD A -40C to +85C VDD = 5.0V TBD = To Be Determined. Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. High/Low-Voltage Detect(4)
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21.2 DC Characteristics: Power-Down and Supply Current PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions
PIC18LF2450/4450 (Industrial) PIC18F2450/4450 (Industrial) Param No. IUSBx IPLL IUREG Legend: Note 1:
USB and Related Module Differential Currents (IUSBx, IPLL, IUREG) USB Module TBD TBD mA +25C VDD = 3.3V with On-Chip Transceiver TBD TBD mA +25C VDD = 5.0V 96 MHz PLL TBD TBD TBD +25C VDD = 3.3V (Oscillator Module) TBD TBD TBD +25C VDD = 5.0V USB Internal Voltage TBD TBD TBD +25C VDD = 5.0V Regulator TBD = To Be Determined. Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
2:
3: 4:
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21.3 DC Characteristics: PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Input Low Voltage I/O Ports (except RC4/RC5 in USB mode): D030 D030A D031 D032 D032A D033 VILU VIH with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 and T1OSI OSC1 D+/D- Input Input High Voltage I/O Ports (except RC4/RC5 in USB mode): D040 D040A D041 D042 D042A D043 VIHU IIL D060 D061 D063 IPU D070 Note 1: 2: IPURB with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 and T1OSI OSC1 D+/D- Input Input Leakage Current(2,3) I/O Ports MCLR OSC1 Weak Pull-up Current PORTB Weak Pull-up Current 50 400 A VDD = 5V, VPIN = VSS -- -- -- 1 5 5 A A A VSS VPIN VDD, Pin at high-impedance Vss VPIN VDD Vss VPIN VDD with TTL buffer 0.25 VDD + 0.8V 2.0 0.8 VDD 0.7 VDD 0.8 VDD 0.7 VDD 0.8 VDD 2.4 VDD VDD VDD VDD VDD VDD VDD -- V V V V V V V V XT, HS, HSPLL modes(1) EC mode(1) VDD = 4.35V, USB suspended(5) VDD < 4.5V 4.5V VDD 5.5V with TTL buffer VSS -- VSS VSS VSS VSS VSS -- 0.15 VDD 0.8 0.2 VDD 0.3 VDD 0.2 VDD 0.3 VDD 0.2 VDD 0.8 V V V V V V V V XT, HS, HSPLL modes(1) EC mode(1) VDD = 4.35V, USB suspended(5) VDD < 4.5V 4.5V VDD 5.5V Min Max Units Conditions
DC CHARACTERISTICS Param No. Sym VIL
3: 4: 5:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. D+ parameters per USB Specification 2.0.
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21.3 DC Characteristics: PIC18F2450/4450 (Industrial) PIC18LF2450/4450 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Output Low Voltage I/O Ports (except RC4/RC5 in USB mode) OSC2/CLKO (EC, ECIO modes) VOLU VOH D090 D092 VOHU D+/D- Out Output High Voltage(3) I/O Ports (except RC4/RC5 in USB mode) OSC2/CLKO (EC, ECIO, ECPIO modes) D+/D- Out Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin -- 15 pF In XT and HS modes when external clock is used to drive OSC1 To meet the AC Timing Specifications VDD - 0.7 VDD - 0.7 2.8 -- -- 3.6 V V V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C VDD = 4.35V, USB suspended(5) -- -- -- 0.6 0.6 0.3 V V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C VDD = 4.35V, USB suspended(5) Min Max Units Conditions
DC CHARACTERISTICS Param No. Sym VOL D080 D083
D101 Note 1: 2:
CIO
All I/O pins and OSC2 (in RC mode)
--
50
pF
3: 4: 5:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. D+ parameters per USB Specification 2.0.
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PIC18F2450/4450
TABLE 21-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Internal Program Memory Programming Specifications(1) D110 D113 VPP IDDP Voltage on MCLR/VPP/RE3 pin Supply Current during Programming Program Flash Memory D130 D131 D132 EP VPR VIE Cell Endurance VDD for Read VDD for Block Erase VDD for Externally Timed Erase or Write VDD for Self-Timed Write ICSP Block Erase Cycle Time ICSP Erase or Write Cycle Time (externally timed) Self-Timed Write Cycle Time 10K VMIN 4.5 3.0 VMIN -- 1 -- 40 100K -- -- -- -- 4 -- 2 100 -- 5.5 5.5 5.5 5.5 -- -- -- -- E/W -40C to +85C V V V V ms ms ms Year Provided no other specifications are violated VMIN = Minimum operating voltage Using ICSPTM port Using ICSP port VMIN = Minimum operating voltage VDD > 4.5V VDD > 4.5V 9.00 -- -- -- 13.25 10 V mA (Note 2) Min Typ Max Units Conditions DC Characteristics Param No. Sym
D132A VIW D132B VPEW D133 TIE
D133A TIW D133A TIW D134
TRETD Characteristic Retention
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Required only if Single-Supply Programming is disabled.
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TABLE 21-2:
Param No. D313
USB MODULE SPECIFICATIONS
Operating Conditions: -40C < TA < +85C (unless otherwise stated). Sym VUSB Characteristic USB Voltage Min 3.0 Typ -- Max 3.6 Units V Comments Voltage on bus must be in this range for proper USB operation VSS VPAD VDD; pin at high impedance For VUSB range For VUSB range Voltage range for pad_dp and pad_dm crossover to occur The difference between D+ and D- must exceed this value while VCM is met
D314 D315 D316 D317 D318
IIL VILUSB VIHUSB VCRS VDIFS
Input Leakage on pin Input Low Voltage for USB Buffer Input High Voltage for USB Buffer Crossover Voltage Differential Input Sensitivity
-- -- 2.0 1.3 --
-- -- --
1 0.8 -- 2.0
A V V V V
--
0.2
D319 D320 D321 D322
VCM ZOUT VOL VOH
Differential Common Mode Range Driver Output Impedance Voltage Output Low Voltage Output High
0.8 28 0.0 2.8
-- -- -- --
2.5 44 0.3 3.6
V V V 1.5 k load connected to 3.6V 15 k load connected to ground
TABLE 21-3:
USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40C < TA < +85C (unless otherwise stated). Param No. D323 D324 Sym Characteristics Min 3.0 220 Typ -- -- Max 3.6 -- Units V nF Must hold sufficient charge for peak load with minimal voltage drop Comments
VUSBANA Regulator Output Voltage* CUSB External Filter Capacitor Value*
*
These parameters are characterized but not tested. Parameter numbers not yet assigned for these specifications.
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FIGURE 21-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
VDD VHLVD For VDIRMAG = 1:
(HLVDIF set by hardware)
(HLVDIF can be cleared in software)
VHLVD For VDIRMAG = 0: VDD
HLVDIF
TABLE 21-4:
HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. D420 Sym Characteristic HLVD Voltage on VDD HLVDL<3:0> = 0000 Transition High-to-Low HLVDL<3:0> = 0001 HLVDL<3:0> = 0010 HLVDL<3:0> = 0011 HLVDL<3:0> = 0100 HLVDL<3:0> = 0101 HLVDL<3:0> = 0110 HLVDL<3:0> = 0111 HLVDL<3:0> = 1000 HLVDL<3:0> = 1001 HLVDL<3:0> = 1010 HLVDL<3:0> = 1011 HLVDL<3:0> = 1100 HLVDL<3:0> = 1101 HLVDL<3:0> = 1110 Min 2.06 2.12 2.24 2.32 2.47 2.65 2.74 2.96 3.22 3.37 3.52 3.70 3.90 4.11 4.36 Typ 2.17 2.23 2.36 2.44 2.60 2.79 2.89 3.12 3.39 3.55 3.71 3.90 4.11 4.33 4.59 Max 2.28 2.34 2.48 2.56 2.73 2.93 3.04 3.28 3.56 3.73 3.90 4.10 4.32 4.55 4.82 Units V V V V V V V V V V V V V V V Conditions
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21.4
21.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc ck dt io CCP1 CLKO Data in I/O port
T
Time
mc osc wr t0 t1
MCLR OSC1 WR T0CKI T1CKI
:Uppercase Letters and their meanings S F Fall H High I Invalid (High-Impedance) L Low
P R V Z High Low
Period Rise Valid High-Impedance High Low
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21.4.2 TIMING CONDITIONS
Note: The temperature and voltages specified in Table 21-5 apply to all timing specifications unless otherwise noted. Figure 21-4 specifies the load conditions for the timing specifications. Because of space limitations, the generic terms "PIC18FXXXX" and "PIC18LFXXXX" are used throughout this section to refer to the PIC18F2450/4450 and PIC18LF2450/ 4450 families of devices specifically and only those devices.
TABLE 21-5:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Operating voltage VDD range as described in DC spec Section 21.1 and Section 21.3 . LF parts operate for industrial temperatures only.
AC CHARACTERISTICS
FIGURE 21-4:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 VDD/2 CL VSS Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports Load Condition 2
RL
Pin
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21.4.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 21-5:
OSC1
1 2 3 3 4 4
CLKO
TABLE 21-6:
Param. No. 1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKI Frequency(1) Oscillator Frequency(1) Min DC 0.1 4 4 Max 48 4 25 48 -- 10,000 250 250 -- -- -- 20 7.5 Units MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns Conditions EC, ECIO Oscillator mode XT, XTPLL Oscillator mode HS Oscillator mode HSPLL Oscillator mode EC, ECIO Oscillator mode XT Oscillator mode HS Oscillator mode HSPLL Oscillator mode TCY = 4/FOSC XT Oscillator mode HS Oscillator mode XT Oscillator mode HS Oscillator mode
Symbol FOSC
1
TOSC
External CLKI Period(1) Oscillator Period(1)
20.8 250 25 20.8
2 3 4 Note 1:
TCY TosL, TosH TosR, TosF
Instruction Cycle Time(1) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time
83.3 30 10 -- --
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
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TABLE 21-7:
Param No. F10 F11 F12 F13 Sym
PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Characteristic Min 4 -- -- -0.25 Typ -- 96 -- -- Max 48 -- 2 +0.25 Units MHz MHz ms % Conditions
FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency trc CLK PLL Start-up Time (Lock Time) CLKO Stability (Jitter)
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 21-8:
AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F2450/4450 (INDUSTRIAL) PIC18LF2450/4450 (INDUSTRIAL)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Min Typ Max Units Conditions
PIC18LF2450/4450 (Industrial) PIC18F2450/4450 (Industrial) Param No.
INTRC Accuracy @ Freq = 31 kHz(1) PIC18LF2450/4450 26.562 PIC18F2450/4450 26.562 Legend: Note 1: 2: -- -- 35.938 35.938 kHz kHz -40C to +85C -40C to +85C VDD = 2.7-3.3V VDD = 4.5-5.5V
Shading of rows is to assist in readability of the table. INTRC frequency after calibration. Change of INTRC frequency as VDD changes.
FIGURE 21-6:
CLKO AND I/O TIMING
Q4 Q1 Q2 Q3
OSC1 10 CLKO 12 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 Note: Refer to Figure 21-4 for load conditions. 15 New Value 19 18 16 11
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TABLE 21-9:
Param No. 10 11 12 13 14 15 16 17 18 18A 19 20 20A 21 21A 22 23 TINP TRBP INT Pin High or Low Time RB7:RB4 Change INT High or Low Time TioF Port Output Fall Time
CLKO AND I/O TIMING REQUIREMENTS
Characteristic Min -- -- -- -- -- 0.25 TCY + 25 0 -- 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5 TCY + 20 -- -- 150 -- -- -- 25 60 25 60 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD = 2.0V VDD = 2.0V VDD = 2.0V (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
Symbol
TosH2ckL OSC1 to CLKO TosH2ckH OSC1 to CLKO TckR TckF TckL2ioV TckH2ioI TosH2ioI CLKO Rise Time CLKO Fall Time CLKO to Port Out Valid Port In Hold after CLKO OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) Port Output Rise Time PIC18FXXXX PIC18LFXXXX
TioV2ckH Port In Valid before CLKO TosH2ioV OSC1 (Q1 cycle) to Port Out Valid
TioV2osH Port Input Valid to OSC1 (I/O in setup time) TioR PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
FIGURE 21-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR PWRT Time-out Oscillator Time-out Internal Reset Watchdog Timer Reset 34 I/O pins Note: Refer to Figure 21-4 for load conditions. 33 32 30
31 34
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FIGURE 21-8:
VDD
BROWN-OUT RESET TIMING
BVDD 35 VBGAP = 1.2V
VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable
36
TABLE 21-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Param. Symbol No. 30 31 32 33 34 35 36 37 38 39 TmcL TWDT TOST TPWRT TIOZ TBOR TIRVST TLVD TCSD TIOBST Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no postscaler) Oscillator Start-up Timer Period Power-up Timer Period I/O High-Impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become Stable Low-Voltage Detect Pulse Width CPU Start-up Time Time for INTRC to Stabilize Min 2 -- 1024 TOSC -- -- 200 -- 200 5 -- Typ -- 4.00 -- 65.5 2 -- 20 -- -- 1 Max -- TBD 1024 TOSC TBD -- -- 50 -- 10 -- Units s ms -- ms s s s s s ms VDD VLVD VDD BVDD (see D005) TOSC = OSC1 period Conditions
Legend: TBD = To Be Determined
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FIGURE 21-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42 T1OSO/T1CKI
45
46
47 TMR0 or TMR1 Note: Refer to Figure 21-4 for load conditions.
48
TABLE 21-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param Symbol No. 40 41 42 Tt0H Tt0L Tt0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No prescaler With prescaler No prescaler With prescaler No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 10 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY + 20 10 25 30 50 0.5 TCY + 5 10 25 30 50 Greater of: 20 ns or (TCY + 40)/N 60 DC 2 TOSC Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (1, 2, 4,..., 256) Conditions
45
Tt1H
T1CKI High Time
Synchronous, no prescaler Synchronous, with prescaler Asynchronous PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns VDD = 2.0V N = prescale value (1, 2, 4, 8) VDD = 2.0V VDD = 2.0V VDD = 2.0V
46
Tt1L
T1CKI Low Time
Synchronous, no prescaler Synchronous, with prescaler Asynchronous PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
47
Tt1P
T1CKI Input Period
Synchronous
Asynchronous Ft1 48 T1CKI Oscillator Input Frequency Range Tcke2tmrI Delay from External T1CKI Clock Edge to Timer Increment
-- 50 7 TOSC
ns kHz --
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FIGURE 21-10: CAPTURE/COMPARE/PWM TIMINGS (CCP MODULE)
CCP1 (Capture Mode)
50 52
51
CCP1 (Compare or PWM Mode) 53 Note: Refer to Figure 21-4 for load conditions. 54
TABLE 21-12: CAPTURE/COMPARE/PWM REQUIREMENTS
Param Symbol No. 50 TccL CCP1 Input Low Time Characteristic No prescaler With prescaler PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX Min 0.5 TCY + 20 10 20 0.5 TCY + 20 10 20 3 TCY + 40 N PIC18FXXXX PIC18LFXXXX 54 TccF CCP1 Output Fall Time PIC18FXXXX PIC18LFXXXX -- -- -- -- Max -- -- -- -- -- -- -- 25 45 25 45 Units ns ns ns ns ns ns ns ns ns ns ns VDD = 2.0V VDD = 2.0V VDD = 2.0V N = prescale value (1, 4 or 16) VDD = 2.0V Conditions
51
TccH
CCP1 Input High Time
No prescaler With prescaler
52 53
TccP TccR
CCP1 Input Period CCP1 Output Fall Time
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PIC18F2450/4450
FIGURE 21-11: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK pin RC7/RX/DT pin 120 Note:
121
121
122
Refer to Figure 21-4 for load conditions.
TABLE 21-13: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param No. 120 Symbol Characteristic Min Max Units Conditions
TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid Tckrf Tdtrf Clock Out Rise Time and Fall Time (Master mode) Data Out Rise Time and Fall Time
PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
-- -- -- -- -- --
40 100 20 50 20 50
ns ns ns ns ns ns VDD = 2.0V VDD = 2.0V VDD = 2.0V
121 122
FIGURE 21-12:
RC6/TX/CK pin RC7/RX/DT pin
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126 Note: Refer to Figure 21-4 for load conditions.
TABLE 21-14: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param. No. 125 126 Symbol Characteristic Min Max Units Conditions
TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Hold before CK (DT hold time) TCKL2DTL Data Hold after CK (DT hold time)
10 15
-- --
ns ns
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FIGURE 21-13: USB SIGNAL TIMING
USB Data Differential Lines 90% VCRS 10% TLR, TFR TLF, TFF
TABLE 21-15: USB LOW-SPEED TIMING REQUIREMENTS
Param No. Symbol TLR TLF TLRFM Characteristic Transition Rise Time Transition Fall Time Rise/Fall Time Matching Min 75 75 80 Typ -- -- -- Max 300 300 125 Units ns ns % Conditions CL = 200 to 600 pF CL = 200 to 600 pF
TABLE 21-16: USB FULL-SPEED REQUIREMENTS
Param No. Symbol TFR TFF TFRFM Characteristic Transition Rise Time Transition Fall Time Rise/Fall Time Matching Min 4 4 90 Typ -- -- -- Max 20 20 111.1 Units ns ns % Conditions CL = 50 pF CL = 50 pF
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TABLE 21-17: A/D CONVERTER CHARACTERISTICS: PIC18F2450/4450 (INDUSTRIAL) PIC18LF2450/4450 (INDUSTRIAL)
Param Symbol No. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A30 A50 NR EIL EDL EOFF EGN -- VREF VREFH VREFL VAIN ZAIN IREF Characteristic Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity Reference Voltage Range (VREFH - VREFL) Reference Voltage High Reference Voltage Low Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current(2) 1.8 3 VSS VSS - 0.3V VREFL -- -- -- Min -- -- -- -- -- Typ -- -- -- -- -- Guaranteed(1) -- -- -- -- -- -- -- -- -- -- VREFH VDD - 3.0V VREFH 2.5 5 150 Max 10 <1 <1 <1.5 <1 Units bit Conditions VREF 3.0V
LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V -- V V V V V k A A During VAIN acquisition. During A/D conversion cycle. VSS VAIN VREF VDD < 3.0V VDD 3.0V
Note 1: 2:
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
FIGURE 21-14:
A/D CONVERSION TIMING
BSF ADCON0, GO (Note 2) Q4 130 A/D CLK 132 131
A/D DATA
9
8
7
...
...
2
1
0
ADRES
OLD_DATA
NEW_DATA TCY(1) DONE
ADIF GO SAMPLING STOPPED
SAMPLE
Note
1: 2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
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TABLE 21-18: A/D CONVERSION REQUIREMENTS
Param Symbol No. 130 TAD Characteristic A/D Clock Period PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX 131 132 135 137 TCNV TACQ TSWC TDIS Conversion Time (not including acquisition time)(2) Acquisition Time(3) Switching Time from Convert Sample Discharge Time Min 0.7 1.4 TBD TBD 11 1.4 TBD -- 0.2 Max 25.0(1) 25.0 1 3 12 -- -- (Note 4) -- s
(1)
Units s s s s TAD s s
Conditions TOSC based, VREF 3.0V VDD = 2.0V, TOSC based, VREF full range A/D RC mode VDD = 2.0V, A/D RC mode
-40C to +85C 0C to +85C
Legend: Note 1: 2: 3: 4:
TBD = To Be Determined The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. ADRES registers may be read on the following TCY cycle. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. On the following cycle of the device clock.
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22.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Graphs and tables are not available at this time.
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NOTES:
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23.0
23.1
PACKAGING INFORMATION
Package Marking Information
28-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F2450-I/SP e3 0510017
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F2450-E/SO e3 0510017
28-Lead QFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
18F2450 -I/ML e3 0510017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
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PIC18F2450/4450
Package Marking Information (Continued)
40-Lead PDIP
XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F4450-I/P e3 0510017
44-Lead TQFP
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC18F4450 -I/PT e3 0510017
44-Lead QFN
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC18F4450 -I/ML e3 0510017
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PIC18F2450/4450
23.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-line (SP) - 300 mil Body (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1 B p
c eB
Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN
INCHES* NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 .310 .285 1.365 .130 .012 .053 .019 .350 .325 .295 1.385 .135 .015 .065 .022 .430 .150 .130 .160 .135 MAX MIN
MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 3.81 3.30 4.06 3.43 MAX
5 10 15 5 10 15 Mold Draft Angle Bottom 5 10 15 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070
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28-Lead Plastic Small Outline (SO) - Wide, 300 mil Body (SOIC)
E E1 p
D
B n h 45 c A Units Dimension Limits n p L A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 A2 2 1
MAX Number of Pins Pitch Overall Height A .093 .104 2.64 Molded Package Thickness A2 .088 .094 2.39 Standoff A1 .004 .012 0.30 Overall Width E .394 .420 10.67 Molded Package Width E1 .288 .299 7.59 Overall Length D .695 .712 18.08 Chamfer Distance h .010 .029 0.74 Foot Length L .016 .050 1.27 Foot Angle Top 0 8 8 c Lead Thickness .009 .013 0.33 Lead Width B .014 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052
MIN
MAX
MIN
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28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) - With 0.55 mm Contact Length (Saw Singulated)
E EXPOSED METAL PAD (NOTE 2) e E2
D
D2
b
2 1 n OPTIONAL INDEX ALTERNATE INDEX INDICATORS SEE DETAIL L K
TOP VIEW
AREA
(NOTE 1)
BOTTOM VIEW
A1 A
DETAIL ALTERNATE PAD OUTLINE
MILLIMETERS* MAX 28 MIN NOM 28 0.65 BSC .039 .002 .240 .169 .240 .169 .013 .024 - 0.80 0.00 5.90 3.89 5.90 3.89 0.23 0.45 0.20 0.90 0.02 0.20 REF 6.00 4.24 6.00 4.24 0.28 0.55 - 6.10 4.29 6.10 4.29 0.33 0.65 - 1.00 0.05 MAX NOM
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad * Controlling Parameter Significant Characteristic n e A A1 A3 E E2 D D2 L K .232 .153 .232 .153 .009 .018 .008 .031 .000 MIN
INCHES
.026 BSC .035 .001 .008 REF .236 .167 .236 .167 .011 .022 -
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exposed pad varies according to die attach paddle size. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC equivalent: MO-220 Drawing No. C04-105
Revised 09-12-05
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40-Lead Plastic Dual In-line (P) - 600 mil Body (PDIP)
E1
D
n E
2 1
A c eB Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150 A1 B1 B p MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10
A2 L
MAX Number of Pins Pitch Top to Seating Plane A .160 .190 4.83 Molded Package Thickness A2 .140 .160 4.06 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .625 15.88 Molded Package Width E1 .530 .545 .560 14.22 Overall Length D 2.045 2.058 2.065 52.45 Tip to Seating Plane L .120 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .030 .050 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 Overall Row Spacing eB .620 .650 .680 17.27 Mold Draft Angle Top 5 10 15 15 Mold Draft Angle Bottom 5 10 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016
MIN
MAX
MIN
DS39760A-page 300
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44-Lead Plastic Thin-Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E E1 #leads=n1 p
D1
D
2 1 B n CH x 45 A c
L Units Dimension Limits n p n1 A A2 A1 L F
A1 F INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 REF.
A2
MIN
MAX
MIN
Number of Pins
MILLIMETERS* NOM 44 0.80 11 1.10 1.00 0.10 0.60 1.00 REF.
MAX
Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference)
.039 .037 .002 .018
.047 .041 .006 .030
1.00 0.95 0.05 0.45
1.20 1.05 0.15 0.75
Foot Angle 0 3.5 7 0 3.5 7 Overall Width E .463 .472 .482 11.75 12.00 12.25 Overall Length D .463 .472 .482 11.75 12.00 12.25 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 c Lead Thickness .004 .006 .008 0.09 0.15 0.20 Lead Width B .012 .015 .017 0.30 0.38 0.44 CH .025 .035 .045 0.64 0.89 1.14 Pin 1 Corner Chamfer 5 10 15 5 10 15 Mold Draft Angle Top 5 10 15 5 10 15 Mold Draft Angle Bottom * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MS-026 Revised 07-22-05 Drawing No. C04-076
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44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
E
EXPOSED METAL PAD (NOTE 2)
K
p
D
D2
2 1 n OPTIONAL INDEX AREA (NOTE 1) PIN 1 INDEX ON EXPOSED PAD (PROFILE MAY VARY)
B
E2 L
TOP VIEW
BOTTOM VIEW
DETAIL: CONTACT VARIANTS
A A3 Units Dimension Limits Number of Contacts Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed-Pad * Controlling Parameter Significant Characteristic Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exposed pad varies according to die attach paddle size. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC equivalent: M0-220 Drawing No. C04-103 n p A A1 A3 E E2 D D2 B L K .309 .236 .309 .236 .008 .014 .014 .031 .000 MIN A1 INCHES NOM 44 .026 BSC .035 .001 .010 REF .315 .258 .315 .258 .013 .016 .321 .260 .321 .260 .013 .019 7.85 5.99 7.85 5.99 0.20 0.35 0.20 .039 .002 0.80 0 0.65 BSC 0.90 0.02 0.25 REF 8.00 6.55 8.00 6.55 0.33 0.40 8.15 6.60 8.15 6.60 0.35 0.48 1.00 0.05 MAX MIN MILLIMETERS* NOM 44 MAX
Revised 09-12-05
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APPENDIX A: REVISION HISTORY APPENDIX B:
Revision A (January 2006)
Original data sheet for PIC18F2450/4450 devices.
DEVICE DIFFERENCES
The differences between the devices listed in this data sheet are shown in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
PIC18F2450 16384 8192 13 Ports A, B, C, (E) 1 10 input channels 28-pin SDIP 28-pin SOIC 28-pin QFN PIC18F4450 16384 8192 13 Ports A, B, C, D, E 1 13 input channels 40-pin PDIP 44-pin TQFP 44-pin QFN
Features Program Memory (Bytes) Program Memory (Instructions) Interrupt Sources I/O Ports Capture/Compare/PWM Modules 10-bit Analog-to-Digital Module Packages
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APPENDIX C: CONVERSION CONSIDERATIONS APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES
This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable
This section discusses how to migrate from a Baseline device (i.e., PIC16C5X) to an Enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available
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APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES
A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18C442". The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716.
A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18CXXX Migration". This Application Note is available as Literature Number DS00726.
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NOTES:
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INDEX
A
A/D ................................................................................... 173 Acquisition Requirements ........................................ 178 ADCON0 Register .................................................... 173 ADCON1 Register .................................................... 173 ADCON2 Register .................................................... 173 ADRESH Register ............................................ 173, 176 ADRESL Register .................................................... 173 Analog Port Pins, Configuring .................................. 180 Associated Registers ............................................... 182 Configuring the Module ............................................ 177 Conversion Clock (TAD) ........................................... 179 Conversion Requirements ....................................... 292 Conversion Status (GO/DONE Bit) .......................... 176 Conversions ............................................................. 181 Converter Characteristics ........................................ 291 Converter Interrupt, Configuring .............................. 177 Discharge ................................................................. 181 Operation in Power-Managed Modes ...................... 180 Selecting and Configuring Acquisition Time ............ 179 Special Event Trigger (CCP1) .................................. 182 Use of the CCP1 Trigger .......................................... 182 Absolute Maximum Ratings ............................................. 265 AC (Timing) Characteristics ............................................. 281 Load Conditions for Device Timing Specifications ....................................... 282 Parameter Symbology ............................................. 281 Temperature and Voltage Specifications ................. 282 Timing Conditions .................................................... 282 AC Characteristics Internal RC Accuracy ............................................... 284 ADCON0 Register ............................................................ 173 GO/DONE Bit ........................................................... 176 ADCON1 Register ............................................................ 173 ADCON2 Register ............................................................ 173 ADDFSR .......................................................................... 254 ADDLW ............................................................................ 217 ADDULNK ........................................................................ 254 ADDWF ............................................................................ 217 ADDWFC ......................................................................... 218 ADRESH Register ............................................................ 173 ADRESL Register .................................................... 173, 176 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 218 ANDWF ............................................................................ 219 Assembler MPASM Assembler .................................................. 262 Auto-Wake-up on Sync Break Character ......................... 166 Fail-Safe Clock Monitor ........................................... 204 Generic I/O Port ......................................................... 99 High/Low-Voltage Detect with External Input .......... 184 Interrupt Logic ............................................................ 86 On-Chip Reset Circuit ................................................ 41 PIC18F2450 .............................................................. 10 PIC18F4450 .............................................................. 11 PLL (HS Mode) .......................................................... 26 PWM Operation (Simplified) .................................... 127 Reads from Flash Program Memory ......................... 77 Table Read Operation ............................................... 73 Table Write Operation ............................................... 74 Table Writes to Flash Program Memory .................... 79 Timer0 in 16-Bit Mode ............................................. 112 Timer0 in 8-Bit Mode ............................................... 112 Timer1 ..................................................................... 116 Timer1 (16-Bit Read/Write Mode) ............................ 116 Timer2 ..................................................................... 122 USB Interrupt Logic Funnel ..................................... 143 USB Peripheral and Options ................................... 129 Watchdog Timer ...................................................... 201 BN .................................................................................... 220 BNC ................................................................................. 221 BNN ................................................................................. 221 BNOV .............................................................................. 222 BNZ ................................................................................. 222 BOR. See Brown-out Reset. BOV ................................................................................. 225 BRA ................................................................................. 223 Brown-out Reset (BOR) ..................................................... 44 Detecting ................................................................... 44 Disabling in Sleep Mode ............................................ 44 Software Enabled ...................................................... 44 BSF .................................................................................. 223 BTFSC ............................................................................. 224 BTFSS ............................................................................. 224 BTG ................................................................................. 225 BZ .................................................................................... 226
C
C Compilers MPLAB C18 ............................................................. 262 MPLAB C30 ............................................................. 262 CALL ................................................................................ 226 CALLW ............................................................................ 255 Capture (CCP Module) .................................................... 124 Associated Registers ............................................... 126 CCP1 Pin Configuration .......................................... 124 CCPR1H:CCPR1L Registers .................................. 124 Prescaler ................................................................. 124 Software Interrupt .................................................... 124 Capture/Compare/PWM (CCP) ....................................... 123 Capture Mode. See Capture. CCP Mode and Timer Resources ............................ 124 CCPR1H Register ................................................... 124 CCPR1L Register .................................................... 124 Compare Mode. See Compare. Module Configuration .............................................. 124 Clock Sources .................................................................... 30 Selection Using OSCCON Register .......................... 30 CLRF ............................................................................... 227 CLRWDT ......................................................................... 227
B
BC .................................................................................... 219 BCF .................................................................................. 220 Block Diagrams A/D ........................................................................... 176 Analog Input Model .................................................. 177 Capture Mode Operation ......................................... 124 Compare Mode Operation ....................................... 125 Device Clock .............................................................. 24 EUSART Receive .................................................... 164 EUSART Transmit ................................................... 162 External Power-on Reset Circuit (Slow VDD Power-up) ......................................... 43
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Code Examples 16 x 16 Signed Multiply Routine ................................ 84 16 x 16 Unsigned Multiply Routine ............................ 84 8 x 8 Signed Multiply Routine .................................... 83 8 x 8 Unsigned Multiply Routine ................................ 83 Changing Between Capture Prescalers ................... 124 Computed GOTO Using an Offset Value ................... 56 Erasing a Flash Program Memory Row ..................... 78 Fast Register Stack .................................................... 56 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................ 67 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ............................... 119 Initializing PORTA ...................................................... 99 Initializing PORTB .................................................... 101 Initializing PORTC .................................................... 104 Initializing PORTD .................................................... 107 Initializing PORTE .................................................... 109 Reading a Flash Program Memory Word .................. 77 Saving STATUS, WREG and BSR Registers in RAM ....................................... 97 Writing to Flash Program Memory ....................... 80-81 Code Protection ............................................................... 189 COMF ............................................................................... 228 Compare (CCP Module) ................................................... 125 Associated Registers ............................................... 126 CCP1 Pin Configuration ........................................... 125 CCPR1 Register ...................................................... 125 Software Interrupt .................................................... 125 Special Event Trigger ............................................... 125 Timer1 Mode Selection ............................................ 125 Configuration Bits ............................................................. 190 Configuration Register Protection .................................... 209 Context Saving During Interrupts ....................................... 97 Conversion Considerations .............................................. 304 CPFSEQ .......................................................................... 228 CPFSGT ........................................................................... 229 CPFSLT ........................................................................... 229 Crystal Oscillator/Ceramic Resonator ................................ 25 Customer Change Notification Service ............................ 315 Customer Notification Service .......................................... 315 Customer Support ............................................................ 315 DC Characteristics ........................................................... 276 Power-Down and Supply Current ............................ 268 Supply Voltage ........................................................ 267 DCFSNZ .......................................................................... 231 DECF ............................................................................... 230 DECFSZ .......................................................................... 231 Dedicated ICD/ICSP Port ................................................ 209 Development Support ...................................................... 261 Device Differences ........................................................... 303 Device Overview .................................................................. 7 Features (table) ........................................................... 9 New Core Features ...................................................... 7 Other Special Features ................................................ 8 Direct Addressing .............................................................. 68
E
Effect on Standard PIC MCU Instructions ....................... 258 Electrical Characteristics ................................................. 265 Enhanced Universal Synchronous Receiver Transmitter (USART). See EUSART. Equations A/D Acquisition Time ............................................... 178 A/D Minimum Charging Time ................................... 178 Calculating the Minimum Required A/D Acquisition Time ....................................... 178 Errata ................................................................................... 6 EUSART Asynchronous Mode ................................................ 162 Associated Registers, Receive ........................ 165 Associated Registers, Transmit ....................... 163 Auto-Wake-up on Sync Break ......................... 166 Break Character Sequence ............................. 167 Receiver .......................................................... 164 Setting Up 9-Bit Mode with Address Detect .... 164 Transmitter ...................................................... 162 Baud Rate Generator (BRG) ................................... 157 Associated Registers ....................................... 157 Auto-Baud Rate Detect .................................... 160 Baud Rate Error, Calculating ........................... 157 Baud Rates, Asynchronous Modes ................. 158 High Baud Rate Select (BRGH Bit) ................. 157 Operation in Power-Managed Modes .............. 157 Sampling .......................................................... 157 Synchronous Master Mode ...................................... 168 Associated Registers, Receive ........................ 170 Associated Registers, Transmit ....................... 169 Reception ........................................................ 170 Transmission ................................................... 168 Synchronous Slave Mode ........................................ 171 Associated Registers, Receive ........................ 172 Associated Registers, Transmit ....................... 171 Reception ........................................................ 172 Transmission ................................................... 171 Extended Instruction Set .................................................. 253 ADDFSR .................................................................. 254 ADDULNK ................................................................ 254 and Using MPLAB IDE Tools ................................... 260 CALLW .................................................................... 255 Considerations for Use ............................................ 258 MOVSF .................................................................... 255 MOVSS .................................................................... 256 PUSHL ..................................................................... 256 SUBFSR .................................................................. 257 SUBULNK ................................................................ 257 Syntax ...................................................................... 253 External Clock Input ........................................................... 26
D
Data Addressing Modes ..................................................... 67 Comparing Addressing Modes with the Extended Instruction Set Enabled ................ 71 Direct .......................................................................... 67 Indexed Literal Offset ................................................. 70 BSR Operation ................................................... 72 Instructions Affected .......................................... 70 Mapping the Access Bank ................................. 72 Indirect ....................................................................... 67 Inherent and Literal .................................................... 67 Data Memory ...................................................................... 59 Access Bank .............................................................. 61 and the Extended Instruction Set ............................... 70 Bank Select Register (BSR) ....................................... 59 General Purpose Registers ........................................ 61 Map for PIC18F2450/4450 Devices ........................... 60 Special Function Registers ........................................ 62 Map .................................................................... 62 USB RAM ................................................................... 59 DAW ................................................................................. 230 DC and AC Characteristics Graphs and Tables .................................................. 293
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F
Fail-Safe Clock Monitor ............................................ 189, 204 Interrupts in Power-Managed Modes ....................... 205 POR or Wake-up from Sleep ................................... 205 WDT During Oscillator Failure ................................. 204 Fast Register Stack ............................................................ 56 Firmware Instructions ....................................................... 211 Flash Program Memory ..................................................... 73 Associated Registers ................................................. 81 Control Registers ....................................................... 74 EECON1 and EECON2 ..................................... 74 TABLAT (Table Latch) Register ......................... 76 TBLPTR (Table Pointer) Register ...................... 76 Erase Sequence ........................................................ 78 Erasing ....................................................................... 78 Operation During Code-Protect ................................. 81 Protection Against Spurious Writes ........................... 81 Reading ...................................................................... 77 Table Pointer Boundaries Based on Operation ........................ 76 Table Pointer Boundaries .......................................... 76 Table Reads and Table Writes .................................. 73 Unexpected Termination of Write .............................. 81 Write Sequence ......................................................... 79 Write Verify ................................................................ 81 Writing To ................................................................... 79 FSCM. See Fail-Safe Clock Monitor. Instruction Cycle ................................................................ 57 Clocking Scheme ....................................................... 57 Flow/Pipelining .......................................................... 57 Instruction Set .................................................................. 211 ADDLW .................................................................... 217 ADDWF ................................................................... 217 ADDWF (Indexed Literal Offset mode) .................... 259 ADDWFC ................................................................. 218 ANDLW .................................................................... 218 ANDWF ................................................................... 219 BC ............................................................................ 219 BCF ......................................................................... 220 BN ............................................................................ 220 BNC ......................................................................... 221 BNN ......................................................................... 221 BNOV ...................................................................... 222 BNZ ......................................................................... 222 BOV ......................................................................... 225 BRA ......................................................................... 223 BSF .......................................................................... 223 BSF (Indexed Literal Offset mode) .......................... 259 BTFSC ..................................................................... 224 BTFSS ..................................................................... 224 BTG ......................................................................... 225 BZ ............................................................................ 226 CALL ........................................................................ 226 CLRF ....................................................................... 227 CLRWDT ................................................................. 227 COMF ...................................................................... 228 CPFSEQ .................................................................. 228 CPFSGT .................................................................. 229 CPFSLT ................................................................... 229 DAW ........................................................................ 230 DCFSNZ .................................................................. 231 DECF ....................................................................... 230 DECFSZ .................................................................. 231 General Format ....................................................... 213 GOTO ...................................................................... 232 INCF ........................................................................ 232 INCFSZ .................................................................... 233 INFSNZ .................................................................... 233 IORLW ..................................................................... 234 IORWF ..................................................................... 234 LFSR ....................................................................... 235 MOVF ...................................................................... 235 MOVFF .................................................................... 236 MOVLB .................................................................... 236 MOVLW ................................................................... 237 MOVWF ................................................................... 237 MULLW .................................................................... 238 MULWF ................................................................... 238 NEGF ....................................................................... 239 NOP ......................................................................... 239 Opcode Field Descriptions ...................................... 212 POP ......................................................................... 240 PUSH ....................................................................... 240 RCALL ..................................................................... 241 RESET ..................................................................... 241 RETFIE .................................................................... 242 RETLW .................................................................... 242 RETURN .................................................................. 243 RLCF ....................................................................... 243 RLNCF ..................................................................... 244
G
GOTO .............................................................................. 232
H
Hardware Multiplier ............................................................ 83 Introduction ................................................................ 83 Operation ................................................................... 83 Performance Comparison .......................................... 83 High/Low-Voltage Detect ................................................. 183 Applications .............................................................. 186 Associated Registers ............................................... 187 Characteristics ......................................................... 280 Current Consumption ............................................... 185 Effects of a Reset ..................................................... 187 Operation ................................................................. 184 During Sleep .................................................... 187 Setup ........................................................................ 185 Start-up Time ........................................................... 185 Typical Application ................................................... 186 HLVD. See High/Low-Voltage Detect.
I
I/O Ports ............................................................................. 99 ID Locations ............................................................. 189, 209 Idle Modes ......................................................................... 37 INCF ................................................................................. 232 INCFSZ ............................................................................ 233 In-Circuit Debugger .......................................................... 209 In-Circuit Serial Programming (ICSP) ...................... 189, 209 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 258 Indexed Literal Offset Mode ............................................. 258 Indirect Addressing ............................................................ 68 INFSNZ ............................................................................ 233 Initialization Conditions for all Registers ...................... 49-52
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RRCF ....................................................................... 244 RRNCF .................................................................... 245 SETF ........................................................................ 245 SETF (Indexed Literal Offset mode) ........................ 259 SLEEP ..................................................................... 246 Standard Instructions ............................................... 211 SUBFWB .................................................................. 246 SUBLW .................................................................... 247 SUBWF .................................................................... 247 SUBWFB .................................................................. 248 SWAPF .................................................................... 248 TBLRD ..................................................................... 249 TBLWT ..................................................................... 250 TSTFSZ ................................................................... 251 XORLW .................................................................... 251 XORWF .................................................................... 252 INTCON Register RBIF Bit .................................................................... 101 INTCON Registers ............................................................. 87 Internal Oscillator Block INTHS, INTXT, INTCKO and INTIO Modes ............... 27 Internal RC Oscillator Use with WDT .......................................................... 201 Internet Address ............................................................... 315 Interrupt Sources .............................................................. 189 A/D Conversion Complete ....................................... 177 Capture Complete (CCP) ......................................... 124 Compare Complete (CCP) ....................................... 125 Interrupt-on-Change (RB7:RB4) .............................. 101 INTn Pin ..................................................................... 97 PORTB, Interrupt-on-Change .................................... 97 TMR0 ......................................................................... 97 TMR0 Overflow ........................................................ 113 TMR1 Overflow ........................................................ 115 TMR2 to PR2 Match (PWM) .................................... 127 Interrupts ............................................................................ 85 USB ............................................................................ 85 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ......................................................... 101 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 234 IORWF ............................................................................. 234 IPR Registers ..................................................................... 94 MOVWF ........................................................................... 237 MPLAB ASM30 Assembler, Linker, Librarian .................. 262 MPLAB ICD 2 In-Circuit Debugger .................................. 263 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................... 263 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator ................................... 263 MPLAB Integrated Development Environment Software ............................................. 261 MPLAB PM3 Device Programmer ................................... 263 MPLINK Object Linker/MPLIB Object Librarian ............... 262 MULLW ............................................................................ 238 MULWF ............................................................................ 238
N
NEGF ............................................................................... 239 NOP ................................................................................. 239
O
Oscillator Configuration ..................................................... 23 EC .............................................................................. 23 ECIO .......................................................................... 23 ECPIO ....................................................................... 23 ECPLL ....................................................................... 23 HS .............................................................................. 23 HSPLL ....................................................................... 23 INTCKO ..................................................................... 23 Internal Oscillator Block ............................................. 27 INTHS ........................................................................ 23 INTIO ......................................................................... 23 INTXT ........................................................................ 23 Oscillator Modes and USB Operation ........................ 24 XT .............................................................................. 23 XTPLL ........................................................................ 23 Oscillator Selection .......................................................... 189 Oscillator Settings for USB ................................................ 27 Oscillator Start-up Timer (OST) ................................... 32, 45 Oscillator Switching ........................................................... 30 Oscillator Transitions ......................................................... 30 Oscillator, Timer1 ............................................................. 115
P
Packaging Information ..................................................... 295 Details ...................................................................... 297 Marking .................................................................... 295 PICSTART Plus Development Programmer .................... 264 PIE Registers ..................................................................... 92 Pin Functions MCLR/VPP/RE3 ................................................... 12, 16 NC/ICCK/ICPGC ........................................................ 21 NC/ICDT/ICPGD ........................................................ 21 NC/ICPORTS ............................................................. 21 NC/ICRST/ICVPP ....................................................... 21 OSC1/CLKI .......................................................... 12, 16 OSC2/CLKO/RA6 ................................................ 12, 16 RA0/AN0 .............................................................. 13, 17 RA1/AN1 .............................................................. 13, 17 RA2/AN2/VREF- ................................................... 13, 17 RA3/AN3/VREF+ .................................................. 13, 17 RA4/T0CKI/RCV .................................................. 13, 17 RA5/AN4/HLVDIN ................................................ 13, 17 RB0/AN12/INT0 ................................................... 14, 18 RB1/AN10/INT1 ................................................... 14, 18 RB2/AN8/INT2/VMO ............................................ 14, 18 RB3/AN9/VPO ..................................................... 14, 18 RB4/AN11/KBI0 ................................................... 14, 18
L
LFSR ................................................................................ 235 Low-Voltage ICSP Programming. See Single-Supply ICSP Programming.
M
Master Clear Reset (MCLR) ............................................... 43 Memory Organization ......................................................... 53 Data Memory ............................................................. 59 Program Memory ....................................................... 53 Memory Programming Requirements .............................. 278 Microchip Internet Web Site ............................................. 315 Migration from Baseline to Enhanced Devices ................ 304 Migration from High-End to Enhanced Devices ............... 305 Migration from Mid-Range to Enhanced Devices ............. 305 MOVF ............................................................................... 235 MOVFF ............................................................................. 236 MOVLB ............................................................................. 236 MOVLW ............................................................................ 237 MOVSF ............................................................................ 255 MOVSS ............................................................................ 256
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RB5/KBI1/PGM .................................................... 14, 18 RB6/KBI2/PGC .................................................... 14, 18 RB7/KBI3/PGD .................................................... 14, 18 RC0/T1OSO/T1CKI ............................................. 15, 19 RC1/T1OSI/UOE .................................................. 15, 19 RC2/CCP1 ........................................................... 15, 19 RC4/D-/VM ........................................................... 15, 19 RC5/D+/VP .......................................................... 15, 19 RC6/TX/CK .......................................................... 15, 19 RC7/RX/DT .......................................................... 15, 19 RD0 ............................................................................ 20 RD1 ............................................................................ 20 RD2 ............................................................................ 20 RD3 ............................................................................ 20 RD4 ............................................................................ 20 RD5 ............................................................................ 20 RD6 ............................................................................ 20 RD7 ............................................................................ 20 RE0/AN5 .................................................................... 21 RE1/AN6 .................................................................... 21 RE2/AN7 .................................................................... 21 VDD ...................................................................... 15, 21 VSS ....................................................................... 15, 21 VUSB ..................................................................... 15, 21 Pinout I/O Descriptions PIC18F2450 ............................................................... 12 PIC18F4450 ............................................................... 16 PIR Registers ..................................................................... 90 PLL Frequency Multiplier ................................................... 26 HSPLL, XTPLL, ECPLL and ECPIO Oscillator Modes ................................................ 26 PLL Lock Time-out ............................................................. 45 POP ................................................................................. 240 POR. See Power-on Reset. PORTA Associated Registers ............................................... 100 I/O Summary ............................................................ 100 LATA Register ............................................................ 99 PORTA Register ........................................................ 99 TRISA Register .......................................................... 99 PORTB Associated Registers ............................................... 103 I/O Summary ............................................................ 102 LATB Register .......................................................... 101 PORTB Register ...................................................... 101 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ......................................................... 101 TRISB Register ........................................................ 101 PORTC Associated Registers ............................................... 106 I/O Summary ............................................................ 105 LATC Register ......................................................... 104 PORTC Register ...................................................... 104 TRISC Register ........................................................ 104 PORTD Associated Registers ............................................... 108 I/O Summary ............................................................ 108 LATD Register ......................................................... 107 PORTD Register ...................................................... 107 TRISD Register ........................................................ 107 PORTE Associated Registers ............................................... 110 I/O Summary ............................................................ 110 LATE Register .......................................................... 109 PORTE Register ...................................................... 109 TRISE Register ........................................................ 109 Postscaler, WDT Assignment (PSA Bit) .............................................. 113 Rate Select (T0PS2:T0PS0 Bits) ............................. 113 Power-Managed Modes ..................................................... 33 and A/D Operation ................................................... 180 Clock Sources ........................................................... 33 Clock Transitions and Status Indicators .................... 34 Effects on Various Clock Sources ............................. 32 Entering ..................................................................... 33 Exiting Idle and Sleep Modes .................................... 39 by Interrupt ........................................................ 39 by Reset ............................................................ 39 by WDT Time-out .............................................. 39 Without an Oscillator Start-up Delay ................. 40 Idle ............................................................................. 37 Idle Modes PRI_IDLE .......................................................... 38 RC_IDLE ........................................................... 39 SEC_IDLE ......................................................... 38 Multiple Sleep Commands ......................................... 34 Run Modes ................................................................ 34 PRI_RUN ........................................................... 34 RC_RUN ............................................................ 35 SEC_RUN ......................................................... 34 Selecting .................................................................... 33 Sleep ......................................................................... 37 Summary (table) ........................................................ 33 Power-on Reset (POR) ...................................................... 43 Power-up Delays ............................................................... 32 Power-up Timer (PWRT) ............................................. 32, 45 Prescaler, Timer0 ............................................................ 113 Assignment (PSA Bit) .............................................. 113 Rate Select (T0PS2:T0PS0 Bits) ............................. 113 Prescaler, Timer2 ............................................................ 128 PRI_IDLE Mode ................................................................. 38 PRI_RUN Mode ................................................................. 34 Program Counter ............................................................... 54 PCL, PCH and PCU Registers .................................. 54 PCLATH and PCLATU Registers .............................. 54 Program Memory and the Extended Instruction Set .............................. 70 Code Protection ....................................................... 207 Instructions ................................................................ 58 Two-Word .......................................................... 58 Interrupt Vector .......................................................... 53 Look-up Tables .......................................................... 56 Map and Stack (diagram) .......................................... 53 Reset Vector .............................................................. 53 Program Verification and Code Protection ...................... 206 Associated Registers ............................................... 206 Programming, Device Instructions ................................... 211 Pulse-Width Modulation. See PWM (CCP Module). PUSH ............................................................................... 240 PUSH and POP Instructions .............................................. 55 PUSHL ............................................................................. 256 PWM (CCP Module) Associated Registers ............................................... 128 Duty Cycle ............................................................... 127 Example Frequencies/Resolutions .......................... 128 Period ...................................................................... 127 Setup for PWM Operation ....................................... 128 TMR2 to PR2 Match ................................................ 127
Q
Q Clock ............................................................................ 128
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R
RAM. See Data Memory. RC_IDLE Mode .................................................................. 39 RC_RUN Mode .................................................................. 35 RCALL .............................................................................. 241 RCON Register Bit Status During Initialization .................................... 48 Reader Response ............................................................ 316 Register File Summary ................................................. 63-65 Registers ADCON0 (A/D Control 0) ......................................... 173 ADCON1 (A/D Control 1) ......................................... 174 ADCON2 (A/D Control 2) ......................................... 175 BAUDCON (Baud Rate Control) .............................. 156 BDnSTAT (Buffer Descriptor n Status, CPU Mode) ...................................................... 139 BDnSTAT (Buffer Descriptor n Status, SIE Mode) ........................................................ 140 CCP1CON (Capture/Compare/PWM Control) ............................................................ 123 CONFIG1H (Configuration 1 High) .......................... 192 CONFIG1L (Configuration 1 Low) ............................ 191 CONFIG2H (Configuration 2 High) .......................... 194 CONFIG2L (Configuration 2 Low) ............................ 193 CONFIG3H (Configuration 3 High) .......................... 195 CONFIG4L (Configuration 4 Low) ............................ 196 CONFIG5H (Configuration 5 High) .......................... 197 CONFIG5L (Configuration 5 Low) ............................ 197 CONFIG6H (Configuration 6 High) .......................... 198 CONFIG6L (Configuration 6 Low) ............................ 198 CONFIG7H (Configuration 7 High) .......................... 199 CONFIG7L (Configuration 7 Low) ............................ 199 DEVID1 (Device ID 1) .............................................. 200 DEVID2 (Device ID 2) .............................................. 200 EECON1 (Memory Control 1) .................................... 75 HLVDCON (High/Low-Voltage Detect Control) ................................................. 183 INTCON (Interrupt Control) ........................................ 87 INTCON2 (Interrupt Control 2) ................................... 88 INTCON3 (Interrupt Control 3) ................................... 89 IPR1 (Peripheral Interrupt Priority 1) .......................... 94 IPR2 (Peripheral Interrupt Priority 2) .......................... 95 OSCCON (Oscillator Control) .................................... 31 PIE1 (Peripheral Interrupt Enable 1) .......................... 92 PIE2 (Peripheral Interrupt Enable 2) .......................... 93 PIR1 (Peripheral Interrupt Request (Flag) 1) ............................................................. 90 PIR2 (Peripheral Interrupt Request (Flag) 2) ............................................................. 91 PORTE ..................................................................... 109 RCON (Reset Control) ......................................... 42, 96 RCSTA (Receive Status and Control) ...................... 155 STATUS ..................................................................... 66 STKPTR (Stack Pointer) ............................................ 55 T0CON (Timer0 Control) .......................................... 111 T1CON (Timer1 Control) .......................................... 115 T2CON (Timer2 Control) .......................................... 121 TXSTA (Transmit Status and Control) ..................... 154 UCFG (USB Configuration) ...................................... 132 UCON (USB Control) ............................................... 130 UEIE (USB Error Interrupt Enable) .......................... 147 UEIR (USB Error Interrupt Status) ........................... 146 UEPn (USB Endpoint n Control) .............................. 135 UIE (USB Interrupt Enable) ..................................... 145 UIR (USB Interrupt Status) ...................................... 144 USTAT (USB Status) ............................................... 134 WDTCON (Watchdog Timer Control) ...................... 202 RESET ............................................................................. 241 Reset State of Registers .................................................... 48 Reset Timers ..................................................................... 45 Oscillator Start-up Timer (OST) ................................. 45 PLL Lock Time-out ..................................................... 45 Power-up Timer (PWRT) ........................................... 45 Resets ........................................................................ 41, 189 Brown-out Reset (BOR) ........................................... 189 Oscillator Start-up Timer (OST) ............................... 189 Power-on Reset (POR) ............................................ 189 Power-up Timer (PWRT) ......................................... 189 RETFIE ............................................................................ 242 RETLW ............................................................................ 242 RETURN .......................................................................... 243 Return Address Stack ........................................................ 54 and Associated Registers .......................................... 54 Return Stack Pointer (STKPTR) ........................................ 55 Revision History ............................................................... 303 RLCF ............................................................................... 243 RLNCF ............................................................................. 244 RRCF ............................................................................... 244 RRNCF ............................................................................ 245
S
SEC_IDLE Mode ............................................................... 38 SEC_RUN Mode ................................................................ 34 SETF ................................................................................ 245 Single-Supply ICSP Programming ................................... 210 SLEEP ............................................................................. 246 Sleep OSC1 and OSC2 Pin States ...................................... 32 Sleep Mode ........................................................................ 37 Software Simulator (MPLAB SIM) ................................... 262 Special Event Trigger. See Compare (CCP Module). Special Features of the CPU ........................................... 189 Special ICPORT Features ............................................... 209 Stack Full/Underflow Resets .............................................. 56 STATUS Register .............................................................. 66 SUBFSR .......................................................................... 257 SUBFWB ......................................................................... 246 SUBLW ............................................................................ 247 SUBULNK ........................................................................ 257 SUBWF ............................................................................ 247 SUBWFB ......................................................................... 248 SWAPF ............................................................................ 248
T
T0CON Register PSA Bit .................................................................... 113 T0CS Bit .................................................................. 112 T0PS2:T0PS0 Bits ................................................... 113 T0SE Bit .................................................................. 112 Table Pointer Operations (table) ........................................ 76 Table Reads/Table Writes ................................................. 56 TBLRD ............................................................................. 249 TBLWT ............................................................................. 250 Time-out in Various Situations (table) ................................ 45 Time-out Sequence ........................................................... 45
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Timer0 .............................................................................. 111 16-Bit Mode Timer Reads and Writes ...................... 112 Associated Registers ............................................... 113 Clock Source Edge Select (T0SE Bit) ...................... 112 Clock Source Select (T0CS Bit) ............................... 112 Operation ................................................................. 112 Overflow Interrupt .................................................... 113 Prescaler .................................................................. 113 Switching Assignment ...................................... 113 Prescaler. See Prescaler, Timer0. Timer1 .............................................................................. 115 16-Bit Read/Write Mode ........................................... 117 Associated Registers ....................................... 119, 126 Interrupt .................................................................... 118 Operation ................................................................. 116 Oscillator .......................................................... 115, 117 Layout Considerations ..................................... 118 Low-Power Option ........................................... 117 Using Timer1 as a Clock Source ..................... 117 Overflow Interrupt .................................................... 115 Resetting, Using a Special Event Trigger Output (CCP) ................................................... 118 TMR1H Register ...................................................... 115 TMR1L Register ....................................................... 115 Use as a Real-Time Clock ....................................... 118 Timer2 .............................................................................. 121 Associated Registers ............................................... 122 Interrupt .................................................................... 122 Operation ................................................................. 121 Output ...................................................................... 122 PR2 Register ............................................................ 127 TMR2 to PR2 Match Interrupt .................................. 127 Timing Diagrams A/D Conversion ........................................................ 291 Asynchronous Reception ......................................... 165 Asynchronous Transmission .................................... 163 Asynchronous Transmission (Back to Back) ................................................. 163 Automatic Baud Rate Calculation ............................ 161 Auto-Wake-up Bit (WUE) During Normal Operation ............................................ 166 Auto-Wake-up Bit (WUE) During Sleep ................... 166 BRG Overflow Sequence ......................................... 161 Brown-out Reset (BOR) ........................................... 286 Capture/Compare/PWM (CCP) ................................ 288 CLKO and I/O .......................................................... 284 Clock/Instruction Cycle .............................................. 57 EUSART Synchronous Receive (Master/Slave) ................................................. 289 EUSART Synchronous Transmission (Master/Slave) ................................................. 289 External Clock (All Modes Except PLL) ................... 283 Fail-Safe Clock Monitor ............................................ 205 High/Low-Voltage Detect Characteristics ................ 280 High-Voltage Detect (VDIRMAG = 1) ...................... 186 Low-Voltage Detect (VDIRMAG = 0) ....................... 185 PWM Output ............................................................ 127 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) .................................................. 285 Send Break Character Sequence ............................ 167 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 47 Synchronous Reception (Master Mode, SREN) ..................................... 170 Synchronous Transmission ..................................... 168 Synchronous Transmission (Through TXEN) .......... 169 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) .......................................... 47 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ...................... 46 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ...................... 46 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise TPWRT) .............. 46 Timer0 and Timer1 External Clock .......................... 287 Transition for Entry to Idle Mode ............................... 38 Transition for Entry to SEC_RUN Mode .................... 34 Transition for Entry to Sleep Mode ............................ 37 Transition for Two-Speed Start-up (INTOSC to HSPLL) ........................................ 203 Transition for Wake from Idle to Run Mode .......................................................... 38 Transition for Wake from Sleep (HSPLL) .................. 37 Transition from RC_RUN Mode to PRI_RUN Mode ................................................. 36 Transition from SEC_RUN Mode to PRI_RUN Mode (HSPLL) .................................. 35 Transition to RC_RUN Mode ..................................... 36 USB Signal .............................................................. 290 Timing Diagrams and Specifications ............................... 283 Capture/Compare/PWM Requirements (CCP) ....................................... 288 CLKO and I/O Requirements ................................... 285 EUSART Synchronous Receive Requirements .................................................. 289 EUSART Synchronous Transmission Requirements .................................................. 289 External Clock Requirements .................................. 283 PLL Clock ................................................................ 284 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ........................................ 286 Timer0 and Timer1 External Clock Requirements .................................................. 287 USB Full-Speed Requirements ............................... 290 USB Low-Speed Requirements ............................... 290 Top-of-Stack Access .......................................................... 54 TQFP Packages and Special Features ........................... 209 TSTFSZ ........................................................................... 251 Two-Speed Start-up ................................................. 189, 203 Two-Word Instructions Example Cases ......................................................... 58 TXSTA Register BRGH Bit ................................................................. 157
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U
Universal Serial Bus ........................................................... 59 Address Register (UADDR) ..................................... 136 Associated Registers ............................................... 149 Buffer Descriptor Table ............................................ 137 Buffer Descriptors .................................................... 137 Address Validation ........................................... 140 Assignment in Different Buffering Modes ....................................... 142 BDnSTAT Register (CPU Mode) ..................... 138 BDnSTAT Register (SIE Mode) ....................... 140 Byte Count ....................................................... 140 Example ........................................................... 137 Memory Map .................................................... 141 Ownership ........................................................ 137 Ping-Pong Buffering ......................................... 141 Register Summary ........................................... 142 Status and Configuration ................................. 137 Class Specifications and Drivers ............................. 151 Descriptors ............................................................... 151 Endpoint Control ...................................................... 135 Enumeration ............................................................. 151 External Transceiver ................................................ 131 Eye Pattern Test Enable .......................................... 133 Firmware and Drivers ............................................... 148 Frame Number Registers ......................................... 136 Frames ..................................................................... 150 Internal Transceiver ................................................. 131 Internal Voltage Regulator ....................................... 133 Interrupts .................................................................. 143 and USB Transactions ..................................... 143 Layered Framework ................................................. 150 Oscillator Requirements ........................................... 148 Output Enable Monitor ............................................. 133 Overview .......................................................... 129, 150 Ping-Pong Buffer Configuration ............................... 133 Power ....................................................................... 150 Power Modes ........................................................... 148 Bus Power Only ............................................... 148 Dual Power with Self-Power Dominance ............................................... 148 Self-Power Only ............................................... 148 Pull-up Resistors ...................................................... 133 RAM ......................................................................... 136 Memory Map .................................................... 136 Speed ....................................................................... 151 Status and Control ................................................... 130 Transfer Types ......................................................... 150 UFRMH:UFRML Registers ...................................... 136 USB Internal Voltage Regulator Specifications ................ 279 Module Specifications .............................................. 279 USB. See Universal Serial Bus.
W
Watchdog Timer (WDT) ........................................... 189, 201 Associated Registers ............................................... 202 Control Register ....................................................... 201 During Oscillator Failure .......................................... 204 Programming Considerations .................................. 201 WWW Address ................................................................ 315 WWW, On-Line Support ...................................................... 6
X
XORLW ............................................................................ 251 XORWF ........................................................................... 252
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PIC18F2450/4450
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2006 Microchip Technology Inc.
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DS39760A-page 315
PIC18F2450/4450
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC18F2450/4450 Questions: 1. What are the best features of this document? Y N Literature Number: DS39760A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39760A-page 316
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(c) 2006 Microchip Technology Inc.
PIC18F2450/4450
PIC18F2450/4450 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device PIC18F2450 , PIC18F4450 , PIC18F2450T(2), PIC18F4450(2); VDD range 4.2V to 5.5V PIC18LF2450(1), PIC18LF4450(1), PIC18LF2450(2), PIC18LF4450(2); VDD range 2.0V to 5.5V
(1) (1)
c)
PIC18LF4450-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF2450-I/SO = Industrial temp., SOIC package, Extended VDD limits. PIC18F4450-I/P = Industrial temp., PDIP package, normal VDD limits.
Temperature Range
I E
= =
-40C to +85C (Industrial) -40C to +125C (Extended)
Package
PT SO SP P ML
= = = = =
TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP PDIP QFN
Note 1: 2:
F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel TQFP packages only.
Pattern
QTP, SQTP, Code or Special Requirements (blank otherwise)
(c) 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 317
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
10/31/05
DS39760A-page 318
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(c) 2006 Microchip Technology Inc.

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